ARM: dts: msm: Add initial smmu dt for sdxlemur

#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {

		apps_smmu: apps-smmu@15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x40000>,

			<0x15042000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;

		interconnects = <&system_noc MASTER_APPSS_PROC

				 &mem_noc SLAVE_IMEM_CFG>;

		qcom,active-only;

		periph_tbu: periph_tbu@15045000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15045000 0x1000>,

				<0x15042200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

			interconnects = <&system_noc MASTER_APPSS_PROC

					 &mem_noc SLAVE_IMEM_CFG>;

			qcom,active-only;

		};

		ipa_tbu: ipa_tbu@15049000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x15049000 0x1000>,

				<0x15042208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

			interconnects = <&system_noc MASTER_APPSS_PROC

					&mem_noc SLAVE_IMEM_CFG>;

			qcom,active-only;

		};

	};

	apps_iommu_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x100 0>;

		qcom,iommu-dma = "disabled";

	};

	apps_iommu_coherent_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x101 0>;

		qcom,iommu-dma = "disabled";

		dma-coherent;

	};

};

#include "sdxlemur-pinctrl.dtsi"

#include "sdxlemur-stub-regulator.dtsi"

#include "msm-arm-smmu-sdxlemur.dtsi"

#include "sdxlemur-usb.dtsi"