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Commit e6d66c50 authored by Alison Wang's avatar Alison Wang Committed by Shawn Guo
Browse files

arm64: dts: fsl: Update address-cells and reg properties of cpu nodes 



MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.

Signed-off-by: default avatarAlison Wang <alison.wang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 1a695a90

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 
	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#address-cells = <1>;

		#size-cells = <0>;



		/*
@@ -63,28 +63,28 @@ 
		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;

			reg = <0x2>;

			clocks = <&clockgen 1 0>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			reg = <0x3>;

			clocks = <&clockgen 1 0>;

		};

	};

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 
	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#address-cells = <1>;

		#size-cells = <0>;



		/*
@@ -65,56 +65,56 @@ 
		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x0>;

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x1>;

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

		};



		cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x100>;

			reg = <0x100>;

			clocks = <&clockgen 1 1>;

		};



		cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x101>;

			reg = <0x101>;

			clocks = <&clockgen 1 1>;

		};



		cpu@200 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x200>;

			reg = <0x200>;

			clocks = <&clockgen 1 2>;

		};



		cpu@201 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x201>;

			reg = <0x201>;

			clocks = <&clockgen 1 2>;

		};



		cpu@300 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x300>;

			reg = <0x300>;

			clocks = <&clockgen 1 3>;

		};



		cpu@301 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x301>;

			reg = <0x301>;

			clocks = <&clockgen 1 3>;

		};

	};