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Commit e65fdfd6 authored by Sylvain Munaut's avatar Sylvain Munaut Committed by Paul Mackerras
Browse files

[POWERPC] Separate IRQ config / register set from main header 



There is no need to expose these settings outside the scope
of the interrupt controller code itself.

Signed-off-by: default avatarSylvain Munaut <tnt@246tNt.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent b9cf5d8e

arch/powerpc/platforms/52xx/mpc52xx_pic.c

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include <asm/irq.h>

#include <asm/prom.h>

#include <asm/mpc52xx.h>

#include "mpc52xx_pic.h"



/*

 *

arch/powerpc/platforms/52xx/mpc52xx_pic.h

0 → 100644
+53 −0
Original line number Diff line number Diff line 
/*

 * Header file for Freescale MPC52xx Interrupt controller

 *

 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>

 * Copyright (C) 2003 MontaVista, Software, Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2. This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



#ifndef __POWERPC_SYSDEV_MPC52xx_PIC_H__

#define __POWERPC_SYSDEV_MPC52xx_PIC_H__



#include <asm/types.h>





/* HW IRQ mapping */

#define MPC52xx_IRQ_L1_CRIT	(0)

#define MPC52xx_IRQ_L1_MAIN	(1)

#define MPC52xx_IRQ_L1_PERP	(2)

#define MPC52xx_IRQ_L1_SDMA	(3)



#define MPC52xx_IRQ_L1_OFFSET   (6)

#define MPC52xx_IRQ_L1_MASK     (0x00c0)



#define MPC52xx_IRQ_L2_OFFSET   (0)

#define MPC52xx_IRQ_L2_MASK     (0x003f)



#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)





/* Interrupt controller Register set */

struct mpc52xx_intr {

	u32 per_mask;		/* INTR + 0x00 */

	u32 per_pri1;		/* INTR + 0x04 */

	u32 per_pri2;		/* INTR + 0x08 */

	u32 per_pri3;		/* INTR + 0x0c */

	u32 ctrl;		/* INTR + 0x10 */

	u32 main_mask;		/* INTR + 0x14 */

	u32 main_pri1;		/* INTR + 0x18 */

	u32 main_pri2;		/* INTR + 0x1c */

	u32 reserved1;		/* INTR + 0x20 */

	u32 enc_status;		/* INTR + 0x24 */

	u32 crit_status;	/* INTR + 0x28 */

	u32 main_status;	/* INTR + 0x2c */

	u32 per_status;		/* INTR + 0x30 */

	u32 reserved2;		/* INTR + 0x34 */

	u32 per_error;		/* INTR + 0x38 */

};



#endif /* __POWERPC_SYSDEV_MPC52xx_PIC_H__ */

include/asm-powerpc/mpc52xx.h

+0 −37
Original line number Diff line number Diff line
@@ -19,49 +19,12 @@ 
#endif /* __ASSEMBLY__ */





/* ======================================================================== */

/* HW IRQ mapping                                                           */

/* ======================================================================== */



#define MPC52xx_IRQ_L1_CRIT		(0)

#define MPC52xx_IRQ_L1_MAIN		(1)

#define MPC52xx_IRQ_L1_PERP		(2)

#define MPC52xx_IRQ_L1_SDMA		(3)



#define MPC52xx_IRQ_L1_OFFSET		(6)

#define MPC52xx_IRQ_L1_MASK		(0xc0)



#define MPC52xx_IRQ_L2_OFFSET		(0)

#define MPC52xx_IRQ_L2_MASK		(0x3f)



#define MPC52xx_IRQ_HIGHTESTHWIRQ	(0xd0)





/* ======================================================================== */

/* Structures mapping of some unit register set                             */

/* ======================================================================== */



#ifndef __ASSEMBLY__



/* Interrupt controller Register set */

struct mpc52xx_intr {

	u32 per_mask;		/* INTR + 0x00 */

	u32 per_pri1;		/* INTR + 0x04 */

	u32 per_pri2;		/* INTR + 0x08 */

	u32 per_pri3;		/* INTR + 0x0c */

	u32 ctrl;		/* INTR + 0x10 */

	u32 main_mask;		/* INTR + 0x14 */

	u32 main_pri1;		/* INTR + 0x18 */

	u32 main_pri2;		/* INTR + 0x1c */

	u32 reserved1;		/* INTR + 0x20 */

	u32 enc_status;		/* INTR + 0x24 */

	u32 crit_status;	/* INTR + 0x28 */

	u32 main_status;	/* INTR + 0x2c */

	u32 per_status;		/* INTR + 0x30 */

	u32 reserved2;		/* INTR + 0x34 */

	u32 per_error;		/* INTR + 0x38 */

};



/* Memory Mapping Control */

struct mpc52xx_mmap_ctl {

	u32 mbar;		/* MMAP_CTRL + 0x00 */