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Commit e61c9200 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-5.1-arm-core' of... 

Merge tag 'tegra-for-5.1-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes

ARM: tegra: Core changes for v5.1-rc1

This contains three fixes for resume from LP1 on Tegra30.

* tag 'tegra-for-5.1-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+
  ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30
  ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents d0e1f79a 1c6279b4

arch/arm/mach-tegra/iomap.h

+9 −0
Original line number Diff line number Diff line
@@ -79,15 +79,24 @@ 
#define TEGRA_PMC_BASE			0x7000E400

#define TEGRA_PMC_SIZE			SZ_256



#define TEGRA_MC_BASE			0x7000F000

#define TEGRA_MC_SIZE			SZ_1K



#define TEGRA_EMC_BASE			0x7000F400

#define TEGRA_EMC_SIZE			SZ_1K



#define TEGRA114_MC_BASE		0x70019000

#define TEGRA114_MC_SIZE		SZ_4K



#define TEGRA_EMC0_BASE			0x7001A000

#define TEGRA_EMC0_SIZE			SZ_2K



#define TEGRA_EMC1_BASE			0x7001A800

#define TEGRA_EMC1_SIZE			SZ_2K



#define TEGRA124_MC_BASE		0x70019000

#define TEGRA124_MC_SIZE		SZ_4K



#define TEGRA124_EMC_BASE		0x7001B000

#define TEGRA124_EMC_SIZE		SZ_2K

arch/arm/mach-tegra/sleep-tegra20.S

+0 −2
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ 


#define EMC_CFG				0xc

#define EMC_ADR_CFG			0x10

#define EMC_REFRESH			0x70

#define EMC_NOP				0xdc

#define EMC_SELF_REF			0xe0

#define EMC_REQ_CTRL			0x2b0
@@ -397,7 +396,6 @@ padload_done: 
	mov	r1, #1

	str	r1, [r0, #EMC_NOP]

	str	r1, [r0, #EMC_NOP]

	str	r1, [r0, #EMC_REFRESH]



	emc_device_mask r1, r0

arch/arm/mach-tegra/sleep-tegra30.S

+23 −2
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ 
#define EMC_CFG				0xc

#define EMC_ADR_CFG			0x10

#define EMC_TIMING_CONTROL		0x28

#define EMC_REFRESH			0x70

#define EMC_NOP				0xdc

#define EMC_SELF_REF			0xe0

#define EMC_MRW				0xe8
@@ -45,6 +44,8 @@ 
#define EMC_XM2VTTGENPADCTRL		0x310

#define EMC_XM2VTTGENPADCTRL2		0x314



#define MC_EMEM_ARB_CFG			0x90



#define PMC_CTRL			0x0

#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
@@ -419,6 +420,22 @@ _pll_m_c_x_done: 
	movweq	r0, #:lower16:TEGRA124_EMC_BASE

	movteq	r0, #:upper16:TEGRA124_EMC_BASE



	cmp	r10, #TEGRA30

	moveq	r2, #0x20

	movweq	r4, #:lower16:TEGRA_MC_BASE

	movteq	r4, #:upper16:TEGRA_MC_BASE

	cmp	r10, #TEGRA114

	moveq	r2, #0x34

	movweq	r4, #:lower16:TEGRA114_MC_BASE

	movteq	r4, #:upper16:TEGRA114_MC_BASE

	cmp	r10, #TEGRA124

	moveq	r2, #0x20

	movweq	r4, #:lower16:TEGRA124_MC_BASE

	movteq	r4, #:upper16:TEGRA124_MC_BASE



	ldr	r1, [r5, r2]		@ restore MC_EMEM_ARB_CFG

	str	r1, [r4, #MC_EMEM_ARB_CFG]



exit_self_refresh:

	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL

	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
@@ -459,7 +476,6 @@ emc_wait_auto_cal_onetime: 
	cmp	r10, #TEGRA30

	streq	r1, [r0, #EMC_NOP]

	streq	r1, [r0, #EMC_NOP]

	streq	r1, [r0, #EMC_REFRESH]



	emc_device_mask r1, r0
@@ -521,6 +537,8 @@ zcal_done: 
	ldr	r1, [r5, #0x0]		@ restore EMC_CFG

	str	r1, [r0, #EMC_CFG]



	emc_timing_update r1, r0



	/* Tegra114 had dual EMC channel, now config the other one */

	cmp	r10, #TEGRA114

	bne	__no_dual_emc_chanl
@@ -546,6 +564,7 @@ tegra30_sdram_pad_address: 
	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA_MC_BASE + MC_EMEM_ARB_CFG				@0x20

tegra30_sdram_pad_address_end:



tegra114_sdram_pad_address:
@@ -562,6 +581,7 @@ tegra114_sdram_pad_address: 
	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c

	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30

	.word	TEGRA114_MC_BASE + MC_EMEM_ARB_CFG			@0x34

tegra114_sdram_pad_adress_end:



tegra124_sdram_pad_address:
@@ -573,6 +593,7 @@ tegra124_sdram_pad_address: 
	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18

	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c

	.word	TEGRA124_MC_BASE + MC_EMEM_ARB_CFG			@0x20

tegra124_sdram_pad_address_end:



tegra30_sdram_pad_size: