Merge tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linux

			The filter can be disabled or changed to another

			driver later using sysfs.

	drm_kms_helper.edid_firmware=[<connector>:]<file>[,[<connector>:]<file>]

	drm.edid_firmware=[<connector>:]<file>[,[<connector>:]<file>]

			Broken monitors, graphic adapters, KVMs and EDIDless

			panels may send no or incorrect EDID data sets.

			This parameter allows to specify an EDID data sets

- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing

  generator. The chip will rely on the sync signals in the DSI data lanes,

  rather than generate its own timings for HDMI output.

- clocks: from common clock binding: reference to the CEC clock.

- clock-names: from common clock binding: must be "cec".

Required nodes:

		reg = <39>;

		interrupt-parent = <&gpio3>;

		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;

		clocks = <&cec_clock>;

		clock-names = "cec";

		adi,input-depth = <8>;

		adi,input-colorspace = "rgb";

Silicon Image SiI9234 HDMI/MHL bridge bindings

Required properties:

	- compatible : "sil,sii9234".

	- reg : I2C address for TPI interface, use 0x39

	- avcc33-supply : MHL/USB Switch Supply Voltage (3.3V)

	- iovcc18-supply : I/O Supply Voltage (1.8V)

	- avcc12-supply : TMDS Analog Supply Voltage (1.2V)

	- cvcc12-supply : Digital Core Supply Voltage (1.2V)

	- interrupts, interrupt-parent: interrupt specifier of INT pin

	- reset-gpios: gpio specifier of RESET pin (active low)

	- video interfaces: Device node can contain two video interface port

			    nodes for HDMI encoder and connector according to [1].

			    - port@0 - MHL to HDMI

			    - port@1 - MHL to connector

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:

	sii9234@39 {

		compatible = "sil,sii9234";

		reg = <0x39>;

		avcc33-supply = <&vcc33mhl>;

		iovcc18-supply = <&vcc18mhl>;

		avcc12-supply = <&vsil12>;

		cvcc12-supply = <&vsil12>;

		reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;

		interrupt-parent = <&gpf3>;

		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				mhl_to_hdmi: endpoint {

					remote-endpoint = <&hdmi_to_mhl>;

				};

			};

			port@1 {

				reg = <1>;

				mhl_to_connector: endpoint {

					remote-endpoint = <&connector_to_mhl>;

				};

			};

		};

	};

* Faraday TV Encoder TVE200

Required properties:

- compatible: must be one of:

	"faraday,tve200"

	"cortina,gemini-tvc", "faraday,tve200"

- reg: base address and size of the control registers block

- interrupts: contains an interrupt specifier for the interrupt

	line from the TVE200

- clock-names: should contain "PCLK" for the clock line clocking the

	silicon and "TVE" for the 27MHz clock to the video driver

- clocks: contains phandle and clock specifier pairs for the entries

	in the clock-names property. See

	Documentation/devicetree/bindings/clock/clock-bindings.txt

Optional properties:

- resets: contains the reset line phandle for the block

Required sub-nodes:

- port: describes LCD panel signals, following the common binding

	for video transmitter interfaces; see

	Documentation/devicetree/bindings/media/video-interfaces.txt

	This port should have the properties:

	reg = <0>;

	It should have one endpoint connected to a remote endpoint where

	the display is connected.

Example:

display-controller@6a000000 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "faraday,tve200";

	reg = <0x6a000000 0x1000>;

	interrupts = <13 IRQ_TYPE_EDGE_RISING>;

	resets = <&syscon GEMINI_RESET_TVC>;

	clocks = <&syscon GEMINI_CLK_GATE_TVC>,

		 <&syscon GEMINI_CLK_TVC>;

	clock-names = "PCLK", "TVE";

	port@0 {

		reg = <0>;

		display_out: endpoint {

			remote-endpoint = <&panel_in>;

		};

	};

};

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks.

- clock-names: the following clocks are required:

  * "mdp_core_clk"

  * "iface_clk"

  * "bus_clk"

  * "core_mmss_clk"

  * "byte_clk"

  * "pixel_clk"

  * "core_clk"

  * "mdp_core"

  * "iface"

  * "bus"

  * "core_mmss"

  * "byte"

  * "pixel"

  * "core"

  For DSIv2, we need an additional clock:

   * "src_clk"

- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.

   * "src"

- assigned-clocks: Parents of "byte" and "pixel" for the given platform.

- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided

  by a DSI PHY block. See [1] for details on clock bindings.

- vdd-supply: phandle to vdd regulator device node

- power-domains: Should be <&mmcc MDSS_GDSC>.

- clocks: Phandles to device clocks. See [1] for details on clock bindings.

- clock-names: the following clocks are required:

  * "iface_clk"

  * "iface"

- vddio-supply: phandle to vdd-io regulator device node

Optional properties:

		reg = <0xfd922800 0x200>;

		power-domains = <&mmcc MDSS_GDSC>;

		clock-names =

			"bus_clk",

			"byte_clk",

			"core_clk",

			"core_mmss_clk",

			"iface_clk",

			"mdp_core_clk",

			"pixel_clk";

			"bus",

			"byte",

			"core",

			"core_mmss",

			"iface",

			"mdp_core",

			"pixel";

		clocks =

			<&mmcc MDSS_AXI_CLK>,

			<&mmcc MDSS_BYTE0_CLK>,

		reg =   <0xfd922a00 0xd4>,

			<0xfd922b00 0x2b0>,

			<0xfd922d80 0x7b>;

		clock-names = "iface_clk";

		clock-names = "iface";

		clocks = <&mmcc MDSS_AHB_CLK>;

		#clock-cells = <1>;

		vddio-supply = <&pma8084_l12>;