+2
−10
+6
−2
+1
−28
+0
−11
Loading
Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more
During one of the DP timeout usecases, flush doesn't take
effect due to vid vblank wait failure. As a result, smmu
faults are observed because of fetching the previously
staged planes. This change adds ctl reset in the same
DP atomic commit context to recover and avoid
smmu faults.
Change-Id: I2f9aceca56e27f140607317f7596d6fe0d908af8
Signed-off-by:
Yashwanth <yvulapu@codeaurora.org>