Loading msm/sde/sde_core_irq.c +12 −9 Original line number Diff line number Diff line Loading @@ -464,6 +464,7 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms) return; } if (!sde_in_trusted_vm(sde_kms)) { rc = pm_runtime_get_sync(sde_kms->dev->dev); if (rc < 0) { SDE_ERROR("failed to enable power resource %d\n", rc); Loading @@ -473,7 +474,9 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms) sde_clear_all_irqs(sde_kms); sde_disable_all_irqs(sde_kms); pm_runtime_put_sync(sde_kms->dev->dev); } spin_lock_init(&sde_kms->irq_obj.cb_lock); Loading msm/sde/sde_encoder.c +2 −1 Original line number Diff line number Diff line Loading @@ -2802,6 +2802,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) * and after physical encoder is disabled, to make sure timing * engine is already disabled (for video mode). */ if (!sde_in_trusted_vm(sde_kms)) sde_encoder_dce_disable(sde_enc); sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP); Loading msm/sde/sde_encoder_phys_cmd.c +10 −7 Original line number Diff line number Diff line Loading @@ -1315,13 +1315,16 @@ static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc) return; } if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck) if (!sde_in_trusted_vm(phys_enc->sde_kms)) { if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck) phys_enc->hw_intf->ops.enable_tearcheck( phys_enc->hw_intf, false); else if (phys_enc->hw_pp->ops.enable_tearcheck) phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); } phys_enc->enable_state = SDE_ENC_DISABLED; } Loading msm/sde/sde_encoder_phys_vid.c +3 −0 Original line number Diff line number Diff line Loading @@ -1061,6 +1061,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) return; } if (sde_in_trusted_vm(phys_enc->sde_kms)) goto exit; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); sde_encoder_phys_inc_pending(phys_enc); Loading msm/sde/sde_hw_catalog.c +4 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,7 @@ enum sde_prop { PIPE_ORDER_VERSION, SEC_SID_MASK, BASE_LAYER, TRUSTED_VM_ENV, SDE_PROP_MAX, }; Loading Loading @@ -572,6 +573,7 @@ static struct sde_prop_type sde_prop[] = { PROP_TYPE_U32}, {SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY}, {BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL}, {TRUSTED_VM_ENV, "qcom,sde-trusted-vm-env", false, PROP_TYPE_BOOL}, }; static struct sde_prop_type sde_perf_prop[] = { Loading Loading @@ -3748,6 +3750,8 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg, cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0); cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values, QSEED_HW_VERSION, 0); cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV, 0); } static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) Loading Loading
msm/sde/sde_core_irq.c +12 −9 Original line number Diff line number Diff line Loading @@ -464,6 +464,7 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms) return; } if (!sde_in_trusted_vm(sde_kms)) { rc = pm_runtime_get_sync(sde_kms->dev->dev); if (rc < 0) { SDE_ERROR("failed to enable power resource %d\n", rc); Loading @@ -473,7 +474,9 @@ void sde_core_irq_preinstall(struct sde_kms *sde_kms) sde_clear_all_irqs(sde_kms); sde_disable_all_irqs(sde_kms); pm_runtime_put_sync(sde_kms->dev->dev); } spin_lock_init(&sde_kms->irq_obj.cb_lock); Loading
msm/sde/sde_encoder.c +2 −1 Original line number Diff line number Diff line Loading @@ -2802,6 +2802,7 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) * and after physical encoder is disabled, to make sure timing * engine is already disabled (for video mode). */ if (!sde_in_trusted_vm(sde_kms)) sde_encoder_dce_disable(sde_enc); sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP); Loading
msm/sde/sde_encoder_phys_cmd.c +10 −7 Original line number Diff line number Diff line Loading @@ -1315,13 +1315,16 @@ static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc) return; } if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck) if (!sde_in_trusted_vm(phys_enc->sde_kms)) { if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.enable_tearcheck) phys_enc->hw_intf->ops.enable_tearcheck( phys_enc->hw_intf, false); else if (phys_enc->hw_pp->ops.enable_tearcheck) phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); } phys_enc->enable_state = SDE_ENC_DISABLED; } Loading
msm/sde/sde_encoder_phys_vid.c +3 −0 Original line number Diff line number Diff line Loading @@ -1061,6 +1061,9 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) return; } if (sde_in_trusted_vm(phys_enc->sde_kms)) goto exit; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); sde_encoder_phys_inc_pending(phys_enc); Loading
msm/sde/sde_hw_catalog.c +4 −0 Original line number Diff line number Diff line Loading @@ -201,6 +201,7 @@ enum sde_prop { PIPE_ORDER_VERSION, SEC_SID_MASK, BASE_LAYER, TRUSTED_VM_ENV, SDE_PROP_MAX, }; Loading Loading @@ -572,6 +573,7 @@ static struct sde_prop_type sde_prop[] = { PROP_TYPE_U32}, {SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY}, {BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL}, {TRUSTED_VM_ENV, "qcom,sde-trusted-vm-env", false, PROP_TYPE_BOOL}, }; static struct sde_prop_type sde_perf_prop[] = { Loading Loading @@ -3748,6 +3750,8 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg, cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0); cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values, QSEED_HW_VERSION, 0); cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV, 0); } static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) Loading