Loading qcom/monaco-rumi.dtsi +6 −0 Original line number Diff line number Diff line #include <dt-bindings/clock/qcom,gcc-monaco.h> &soc { timer { clock-frequency = <5000000>; Loading @@ -17,4 +19,8 @@ clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; &cpufreq_hw { clocks = <&bi_tcxo>, <&gcc GPLL0>; }; #include "monaco-stub-regulator.dtsi" qcom/monaco.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; Loading @@ -59,6 +60,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { Loading @@ -77,6 +79,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { Loading @@ -95,6 +98,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { Loading Loading @@ -724,6 +728,24 @@ #reset-cells = <1>; }; cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw"; reg = <0xf521000 0x1400>; reg-names = "freq-domain0"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; qcom,no-accumulative-counter; qcom,max-lut-entries = <12>; #freq-domain-cells = <2>; }; qcom,cpufreq-hw-debug@f521000 { compatible = "qcom,cpufreq-hw-debug"; reg = <0xf521000 0x1400>; reg-names = "domain-top"; qcom,freq-hw-domain = <&cpufreq_hw 0>; }; spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, Loading Loading
qcom/monaco-rumi.dtsi +6 −0 Original line number Diff line number Diff line #include <dt-bindings/clock/qcom,gcc-monaco.h> &soc { timer { clock-frequency = <5000000>; Loading @@ -17,4 +19,8 @@ clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>; }; &cpufreq_hw { clocks = <&bi_tcxo>, <&gcc GPLL0>; }; #include "monaco-stub-regulator.dtsi"
qcom/monaco.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0 4>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x80000>; Loading @@ -59,6 +60,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { Loading @@ -77,6 +79,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { Loading @@ -95,6 +98,7 @@ enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; qcom,freq-domain = <&cpufreq_hw 0 4>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { Loading Loading @@ -724,6 +728,24 @@ #reset-cells = <1>; }; cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw"; reg = <0xf521000 0x1400>; reg-names = "freq-domain0"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; qcom,no-accumulative-counter; qcom,max-lut-entries = <12>; #freq-domain-cells = <2>; }; qcom,cpufreq-hw-debug@f521000 { compatible = "qcom,cpufreq-hw-debug"; reg = <0xf521000 0x1400>; reg-names = "domain-top"; qcom,freq-hw-domain = <&cpufreq_hw 0>; }; spmi_bus: qcom,spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x1c40000 0x1100>, Loading