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Commit e501b3d8 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

agp: Support 64-bit APBASE 



Per the AGP 3.0 spec, APBASE is a standard PCI BAR and may be either 32
bits or 64 bits wide.  Many drivers read APBASE directly, but they only
handled 32-bit BARs.

The PCI core reads APBASE at enumeration-time.  Use pci_bus_address()
instead of reading it again in the driver.  This works correctly for both
32-bit and 64-bit BARs.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 06cf56e4

drivers/char/agp/agp.h

+1 −0
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 


/* Chipset independent registers (from AGP Spec) */

#define AGP_APBASE	0x10

#define AGP_APERTURE_BAR	0



#define AGPSTAT		0x4

#define AGPCMD		0x8

drivers/char/agp/ali-agp.c

+2 −2
Original line number Diff line number Diff line
@@ -85,8 +85,8 @@ static int ali_configure(void) 
	pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));



	/* address to map to */

	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);

	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,

						    AGP_APERTURE_BAR);



#if 0

	if (agp_bridge->type == ALI_M1541) {

drivers/char/agp/amd-k7-agp.c

+1 −3
Original line number Diff line number Diff line
@@ -126,7 +126,6 @@ static int amd_create_gatt_table(struct agp_bridge_data *bridge) 
	unsigned long __iomem *cur_gatt;

	unsigned long addr;

	int retval;

	u32 temp;

	int i;



	value = A_SIZE_LVL2(agp_bridge->current_size);
@@ -149,8 +148,7 @@ static int amd_create_gatt_table(struct agp_bridge_data *bridge) 
	 * used to program the agp master not the cpu

	 */



	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);

	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);

	agp_bridge->gart_bus_addr = addr;



	/* Calculate the agp offset */

drivers/char/agp/amd64-agp.c

+1 −4
Original line number Diff line number Diff line
@@ -269,7 +269,6 @@ static int agp_aperture_valid(u64 aper, u32 size) 
 */

static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)

{

	u32 aper_low, aper_hi;

	u64 aper, nb_aper;

	int order = 0;

	u32 nb_order, nb_base;
@@ -295,9 +294,7 @@ static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap) 
		apsize |= 0xf00;

	order = 7 - hweight16(apsize);



	pci_read_config_dword(agp, 0x10, &aper_low);

	pci_read_config_dword(agp, 0x14, &aper_hi);

	aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);

	aper = pci_bus_address(agp, AGP_APERTURE_BAR);



	/*

	 * On some sick chips APSIZE is 0. This means it wants 4G

drivers/char/agp/ati-agp.c

+4 −5
Original line number Diff line number Diff line
@@ -211,10 +211,10 @@ static int ati_configure(void) 
	else

		pci_write_config_dword(agp_bridge->dev, ATI_RS300_IG_AGPMODE, 0x20000);



	/* address to map too */

	/* address to map to */

	/*

	pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp);

	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	agp_bridge.gart_bus_addr = pci_bus_address(agp_bridge.dev,

						   AGP_APERTURE_BAR);

	printk(KERN_INFO PFX "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr);

	*/

	writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID);
@@ -385,8 +385,7 @@ static int ati_create_gatt_table(struct agp_bridge_data *bridge) 
	 * This is a bus address even on the alpha, b/c its

	 * used to program the agp master not the cpu

	 */

	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);

	addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);

	agp_bridge->gart_bus_addr = addr;



	/* Calculate the agp offset */