Merge "mtd: msm_qpic_nand: Enable Pagescope read feature on sdxlemur" into msm-5.4 (e4fe3f83) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/mtd/devices/msm_qpic_nand.c

+15 −25

Original line number	Diff line number	Diff line
		@@ -1986,6 +1986,8 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from,

		while (rw_params.page_count-- > 0) {

		uint32_t cw_desc_cnt = 1;
		struct sps_command_element curr_ce, start_ce;
		erased_page = false;
		data.addr0 = (rw_params.page << 16) \| rw_params.oob_col;
		data.addr1 = (rw_params.page >> 16) & 0xff;
		@@ -1998,6 +2000,15 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from,
		msm_nand_prep_read_cmd_desc_pagescope(ops, &rw_params,
		&data, info,
		cmd_list, 0);
		start_ce = &cmd_list->cw_desc[cw_desc_cnt].ce[0];
		curr_ce = start_ce;
		cmd_list->cw_desc[cw_desc_cnt].flags = CMD \| INT_UNLCK;
		cmd_list->count++;
		msm_nand_prep_ce(curr_ce, MSM_NAND_AUTO_STATUS_EN(info),
		WRITE, flash_cmd);
		curr_ce++;
		cmd_list->cw_desc[cw_desc_cnt].num_ce = curr_ce - start_ce;

		dma_buffer->xfer.iovec_count = cmd_list->count;
		dma_buffer->xfer.iovec = dma_buffer->cmd_iovec;
		dma_buffer->xfer.iovec_phys = msm_virt_to_dma(chip,
		@@ -2092,31 +2103,7 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from,
		(info->sps.data_prod_stat.index), err);
		goto put_dev;
		}
		/*
		* There is a H/W BUG in qpic 2.0. You should unlock the command
		* pipe only after all the status descriptors are collected on
		* status descriptor pipe (pipe#3).
		*/

		/* Unlock the command pipe now */
		msm_nand_prep_single_desc(sps_cmd,
		MSM_NAND_AUTO_STATUS_EN(info),
		WRITE, flash_cmd, INT_UNLCK);
		err = sps_transfer_one(info->sps.cmd_pipe.handle,
		msm_virt_to_dma(chip, &sps_cmd->ce),
		sizeof(struct sps_command_element),
		NULL, sps_cmd->flags);
		if (err) {
		pr_err("Failed to unlock cmd desc. pipe: %d\n", err);
		goto put_dev;
		}
		err = msm_nand_sps_get_iovec(info->sps.cmd_pipe.handle,
		info->sps.cmd_pipe.index, 1, &iovec_temp);
		if (err) {
		pr_err("Failed to get iovec for cmd desc. err:%d\n",
		err);
		goto put_dev;
		}
		err = msm_nand_put_device(chip->dev);
		mutex_unlock(&info->lock);
		if (err)
		@@ -4480,7 +4467,10 @@ static int msm_nand_probe(struct platform_device *pdev)
		goto free_bam;
		}
		info->nand_chip.qpic_version = qpic_version.qpic_major;
		if (info->nand_chip.qpic_version >= 2) {
		info->nand_chip.qpic_min_version = qpic_version.qpic_minor;
		if (info->nand_chip.qpic_version >= 2 &&
		info->nand_chip.qpic_min_version >= 1) {
		info->nand_chip.caps = MSM_NAND_CAP_PAGE_SCOPE_READ;
		mutex_lock(&info->lock);
		err = msm_nand_get_device(info->nand_chip.dev);
		if (err) {

drivers/mtd/devices/msm_qpic_nand.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -270,7 +270,8 @@ struct msm_nand_chip {
		uint32_t ecc_buf_cfg;
		uint32_t ecc_bch_cfg;
		uint32_t ecc_cfg_raw;
		uint32_t qpic_version; /* To store the qpic controller version */
		uint32_t qpic_version; /* To store the qpic controller major version */
		uint16_t qpic_min_version; /* To store the qpic controller minor version */
		uint32_t caps; /* General host capabilities */
		#define MSM_NAND_CAP_PAGE_SCOPE_READ BIT(0)
		#define MSM_NAND_CAP_MULTI_PAGE_READ BIT(1)