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Commit e499ddf0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "disp: msm: sde: Allow for overriding CP features flush mechanism"

parents 18aab79f deae97dd

msm/sde/sde_color_processing.c

+24 −1
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ struct sde_cp_node { 
	struct list_head active_list;

	struct list_head dirty_list;

	bool is_dspp_feature;

	bool lm_flush_override;

	u32 prop_blob_sz;

	struct sde_irq_callback *irq;

};
@@ -1974,7 +1975,8 @@ void sde_cp_crtc_apply_properties(struct drm_crtc *crtc) 
			dirty_list) {

		sde_cp_crtc_setfeature(prop_node, sde_crtc);

		sde_cp_dspp_flush_helper(sde_crtc, prop_node->feature);

		if (prop_node->is_dspp_feature)

		if (prop_node->is_dspp_feature &&

				!prop_node->lm_flush_override)

			set_dspp_flush = true;

		else

			set_lm_flush = true;
@@ -2636,6 +2638,8 @@ static void dspp_rc_install_property(struct drm_crtc *crtc) 
	char feature_name[256];

	struct sde_kms *kms = NULL;

	struct sde_mdss_cfg *catalog = NULL;

	struct sde_cp_node *prop_node = NULL;

	struct sde_crtc *sde_crtc = NULL;

	u32 version;



	if (!crtc) {
@@ -2643,6 +2647,12 @@ static void dspp_rc_install_property(struct drm_crtc *crtc) 
		return;

	}



	sde_crtc = to_sde_crtc(crtc);

	if (!sde_crtc) {

		DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);

		return;

	}



	kms = get_kms(crtc);

	catalog = kms->catalog;

	version = catalog->dspp[0].sblk->rc.version >> 16;
@@ -2654,6 +2664,19 @@ static void dspp_rc_install_property(struct drm_crtc *crtc) 
				SDE_CP_CRTC_DSPP_RC_MASK,

				sizeof(struct drm_msm_rc_mask_cfg));



		/* Override flush mechanism to use layer mixer flush bits */

		if (!catalog->rc_lm_flush_override)

			break;



		DRM_DEBUG("rc using lm flush override\n");

		list_for_each_entry(prop_node, &sde_crtc->feature_list,

				feature_list) {

			if (prop_node->feature == SDE_CP_CRTC_DSPP_RC_MASK) {

				prop_node->lm_flush_override = true;

				break;

			}

		}



		break;

	default:

		DRM_ERROR("version %d not supported\n", version);

msm/sde/sde_hw_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -4751,6 +4751,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_sui_blendstage = true;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

		sde_cfg->mdss_hw_block_size = 0x158;

		sde_cfg->rc_lm_flush_override = true;

	} else if (IS_SHIMA_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_wb_ubwc = true;

msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -1416,6 +1416,7 @@ struct sde_perf_cfg { 
 * @has_3d_merge_reset Supports 3D merge reset

 * @has_decimation     Supports decimation

 * @has_trusted_vm_support	     Supported HW sharing with trusted VM

 * @rc_lm_flush_override        Support Rounded Corner using layer mixer flush

 * @has_mixer_combined_alpha     Mixer has single register for FG & BG alpha

 * @vbif_disable_inner_outer_shareable     VBIF requires disabling shareables

 * @inline_disable_const_clr     Disable constant color during inline rotate
@@ -1494,6 +1495,7 @@ struct sde_mdss_cfg { 
	bool has_base_layer;

	bool has_demura;

	bool has_trusted_vm_support;

	bool rc_lm_flush_override;

	u32 demura_supported[SSPP_MAX][2];

	u32 qseed_sw_lib_rev;

	u32 qseed_hw_version;