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Commit e4844ded authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-4.15' of... 

Merge tag 'irqchip-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for 4.15 from Marc Zyngier

- GICv4 updates (improved performance, errata workarounds)
- Workaround for Socionext's pre-ITS erratum
- Meson GPIO interrupt controller
- BCM7271 L2 interrupt controller
- GICv3 range selector support
- various cleanups
parents c94fb639 7bdeb7f5

Documentation/arm64/silicon-errata.txt

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@@ -70,6 +70,7 @@ stable kernels. 
|                |                 |                 |                             |

| Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |

| Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |

| Hisilicon      | Hip07           | #161600802      | HISILICON_ERRATUM_161600802 |

|                |                 |                 |                             |

| Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |

| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

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Amlogic meson GPIO interrupt controller



Meson SoCs contains an interrupt controller which is able to watch the SoC

pads and generate an interrupt on edge or level. The controller is essentially

a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge

or level and polarity. It does not expose all 256 mux inputs because the

documentation shows that the upper part is not mapped to any pad. The actual

number of interrupt exposed depends on the SoC.



Required properties:



- compatible : must have "amlogic,meson8-gpio-intc” and either

   “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or

   “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or

   “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)

- interrupt-parent : a phandle to the GIC the interrupts are routed to.

   Usually this is provided at the root level of the device tree as it is

   common to most of the SoC.

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : Specifies the number of cells needed to encode an

   interrupt source. The value must be 2.

- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These

   are the hwirqs used on the parent interrupt controller.



Example:



gpio_interrupt: interrupt-controller@9880 {

	compatible = "amlogic,meson-gxbb-gpio-intc",

		     "amlogic,meson-gpio-intc";

	reg = <0x0 0x9880 0x0 0x10>;

	interrupt-controller;

	#interrupt-cells = <2>;

	meson,channel-interrupts = <64 65 66 67 68 69 70 71>;

};

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

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@@ -75,6 +75,10 @@ These nodes must have the following properties: 
- reg: Specifies the base physical address and size of the ITS

  registers.



Optional:

- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated

  address and size of the pre-ITS window.



The main GIC node must contain the appropriate #address-cells,

#size-cells and ranges properties for the reg property of all ITS

nodes.

Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt

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@@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller 


Required properties:



- compatible: should be "brcm,l2-intc"

- compatible: should be "brcm,l2-intc" for latched interrupt controllers

              should be "brcm,bcm7271-l2-intc" for level interrupt controllers

- reg: specifies the base physical address and size of the registers

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt

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@@ -13,6 +13,9 @@ Required properties: 
    - "renesas,irqc-r8a7793" (R-Car M2-N)

    - "renesas,irqc-r8a7794" (R-Car E2)

    - "renesas,intc-ex-r8a7795" (R-Car H3)

    - "renesas,intc-ex-r8a7796" (R-Car M3-W)

    - "renesas,intc-ex-r8a77970" (R-Car V3M)

    - "renesas,intc-ex-r8a77995" (R-Car D3)

- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in

  interrupts.txt in this directory

- clocks: Must contain a reference to the functional clock.