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Commit e4782dcb authored by Hemant Kumar's avatar Hemant Kumar
Browse files

ARM: dts: msm: Change data size for PCIe write halt 

Update value from 1MB to 256B for PCI RC 1 (3x2).
This is a software workaround to prevent system
bus deadlock issue with concurrent access of
greater than 256B granularity from two PCIe
ports to DDR.

Change-Id: I9461e97a70f58b7ca3070881f208615a0624f5b6
parent 67e5a07c

qcom/lahaina-pcie.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -330,6 +330,7 @@ 
		qcom,boot-option = <0x1>;

		qcom,boot-option = <0x1>;

		qcom,drv-supported;

		qcom,drv-supported;

		qcom,use-19p2mhz-aux-clk;

		qcom,use-19p2mhz-aux-clk;

		qcom,wr-halt-size = <0x8>;

		qcom,no-l0s-supported;

		qcom,no-l0s-supported;

		qcom,slv-addr-space-size = <0x20000000>;

		qcom,slv-addr-space-size = <0x20000000>;

		qcom,ep-latency = <10>;

		qcom,ep-latency = <10>;