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Commit e452b818 authored by Thierry Reding's avatar Thierry Reding
Browse files

clk: tegra: Enable sor1 and sor1_src on Tegra210 



Make the sor1 and sor1_src clocks available on Tegra210. They will be
used by the display driver to support HDMI and DP.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c1273af4

drivers/clk/tegra/clk-tegra210.c

+2 −0
Original line number Diff line number Diff line
@@ -2155,6 +2155,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },

	[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },

	[tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },

	[tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },

	[tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },

	[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },

	[tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },

	[tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },

include/dt-bindings/clock/tegra210-car.h

+1 −1
Original line number Diff line number Diff line
@@ -308,7 +308,7 @@ 
#define TEGRA210_CLK_CLK_OUT_3 279

#define TEGRA210_CLK_BLINK 280

/* 281 */

/* 282 */

#define TEGRA210_CLK_SOR1_SRC 282

/* 283 */

#define TEGRA210_CLK_XUSB_HOST_SRC 284

#define TEGRA210_CLK_XUSB_FALCON_SRC 285