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Commit e431e79b authored by Kim Phillips's avatar Kim Phillips Committed by Ingo Molnar
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perf/x86/amd/ibs: Handle erratum #420 only on the affected CPU family (10h) 



This saves us writing the IBS control MSR twice when disabling the
event.

I searched revision guides for all families since 10h, and did not
find occurrence of erratum #420, nor anything remotely similar:
so we isolate the secondary MSR write to family 10h only.

Also unconditionally update the count mask for IBS Op implementations
that have read & writeable current count (CurCnt) fields in addition
to the MaxCnt field.  These bits were reserved on prior
implementations, and therefore shouldn't have negative impact.

Signed-off-by: default avatarKim Phillips <kim.phillips@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Fixes: c9574fe0 ("perf/x86-ibs: Implement workaround for IBS erratum #420")
Link: https://lkml.kernel.org/r/20191023150955.30292-2-kim.phillips@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 317b96bb

arch/x86/events/amd/ibs.c

+4 −2
Original line number Diff line number Diff line
@@ -377,6 +377,7 @@ static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, 
					  struct hw_perf_event *hwc, u64 config)

{

	config &= ~perf_ibs->cnt_mask;

	if (boot_cpu_data.x86 == 0x10)

		wrmsrl(hwc->config_base, config);

	config &= ~perf_ibs->enable_mask;

	wrmsrl(hwc->config_base, config);
@@ -553,7 +554,8 @@ static struct perf_ibs perf_ibs_op = { 
	},

	.msr			= MSR_AMD64_IBSOPCTL,

	.config_mask		= IBS_OP_CONFIG_MASK,

	.cnt_mask		= IBS_OP_MAX_CNT,

	.cnt_mask		= IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |

				  IBS_OP_CUR_CNT_RAND,

	.enable_mask		= IBS_OP_ENABLE,

	.valid_mask		= IBS_OP_VAL,

	.max_period		= IBS_OP_MAX_CNT << 4,