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Commit e401fa25 authored by Sergey Matyukevich's avatar Sergey Matyukevich Committed by Kalle Valo
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qtnfmac: add support for Topaz chipsets 



This patch adds support for QSR1000/QSR2000 family of chipsets
to qtnfmac_pcie platform driver.

QSR1000/QSR2000 (aka Topaz) is a family of 80MHz, 11ac Wave2,
4x4/2x4/2x2 chips, including single and dual band devices.
Depending on specific chip model and firmware in use, either
STA or both STA and AP modes are supported.

Patch adds Topaz support to qtnfmac_pcie driver. Proper platform
bus will be selected on probing based on chip ID.

Signed-off-by: default avatarIgor Mitsyanko <igor.mitsyanko.os@quantenna.com>
Signed-off-by: default avatarSergey Matyukevich <sergey.matyukevich.os@quantenna.com>
Signed-off-by: default avatarAndrey Shevchenko <ashevchenko@quantenna.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent b7da53cd

drivers/net/wireless/quantenna/qtnfmac/Kconfig

+3 −2
Original line number Original line Diff line number Diff line
@@ -5,7 +5,7 @@ config QTNFMAC 
	default y if QTNFMAC_PCIE=y

	default y if QTNFMAC_PCIE=y





config QTNFMAC_PCIE

config QTNFMAC_PCIE

	tristate "Quantenna QSR10g PCIe support"

	tristate "Quantenna QSR1000/QSR2000/QSR10g PCIe support"

	default n

	default n

	depends on PCI && CFG80211

	depends on PCI && CFG80211

	select QTNFMAC

	select QTNFMAC
@@ -13,7 +13,8 @@ config QTNFMAC_PCIE 
	select CRC32

	select CRC32

	help

	help

	  This option adds support for wireless adapters based on Quantenna

	  This option adds support for wireless adapters based on Quantenna

	  802.11ac QSR10g (aka Pearl) FullMAC chipset running over PCIe.

	  802.11ac QSR10g (aka Pearl) and QSR1000/QSR2000 (aka Topaz)

	  FullMAC chipsets running over PCIe.





	  If you choose to build it as a module, two modules will be built:

	  If you choose to build it as a module, two modules will be built:

	  qtnfmac.ko and qtnfmac_pcie.ko.
 
	  qtnfmac.ko and qtnfmac_pcie.ko.

drivers/net/wireless/quantenna/qtnfmac/Makefile

+2 −1
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@ obj-$(CONFIG_QTNFMAC_PCIE) += qtnfmac_pcie.o 
qtnfmac_pcie-objs += \

qtnfmac_pcie-objs += \

	shm_ipc.o \

	shm_ipc.o \

	pcie/pcie.o \

	pcie/pcie.o \

	pcie/pearl_pcie.o

	pcie/pearl_pcie.o \

	pcie/topaz_pcie.o





qtnfmac_pcie-$(CONFIG_DEBUG_FS) += debug.o
 
qtnfmac_pcie-$(CONFIG_DEBUG_FS) += debug.o

drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -330,6 +330,9 @@ static int qtnf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	case QTN_CHIP_ID_PEARL_C:

	case QTN_CHIP_ID_PEARL_C:

		bus = qtnf_pcie_pearl_alloc(pdev);

		bus = qtnf_pcie_pearl_alloc(pdev);

		break;

		break;

	case QTN_CHIP_ID_TOPAZ:

		bus = qtnf_pcie_topaz_alloc(pdev);

		break;

	default:

	default:

		pr_err("unsupported chip ID 0x%x\n", chipid);

		pr_err("unsupported chip ID 0x%x\n", chipid);

		return -ENOTSUPP;

		return -ENOTSUPP;
@@ -465,7 +468,7 @@ static SIMPLE_DEV_PM_OPS(qtnf_pcie_pm_ops, qtnf_pcie_suspend, 




static const struct pci_device_id qtnf_pcie_devid_table[] = {

static const struct pci_device_id qtnf_pcie_devid_table[] = {

	{

	{

		PCIE_VENDOR_ID_QUANTENNA, PCIE_DEVICE_ID_QTN_PEARL,

		PCIE_VENDOR_ID_QUANTENNA, PCIE_DEVICE_ID_QSR,

		PCI_ANY_ID, PCI_ANY_ID, 0, 0,

		PCI_ANY_ID, PCI_ANY_ID, 0, 0,

	},

	},

	{ },

	{ },

drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -76,6 +76,7 @@ void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv, 
			    struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,

			    struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,

			    const struct qtnf_shm_ipc_int *ipc_int);

			    const struct qtnf_shm_ipc_int *ipc_int);

struct qtnf_bus *qtnf_pcie_pearl_alloc(struct pci_dev *pdev);

struct qtnf_bus *qtnf_pcie_pearl_alloc(struct pci_dev *pdev);

struct qtnf_bus *qtnf_pcie_topaz_alloc(struct pci_dev *pdev);





static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)

static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)

{

{