Merge "msm: camera: csiphy: Update logic for lane enablement" into camera-kernel.lnx.4.0 (e3e11845) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

+540 −266

File changed.

Preview size limit exceeded, changes collapsed.

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c

+15 −9

Original line number	Diff line number	Diff line
		@@ -131,6 +131,7 @@ static int cam_csiphy_component_bind(struct device *dev,
		struct csiphy_device *new_csiphy_dev;
		int32_t rc = 0;
		struct platform_device *pdev = to_platform_device(dev);
		int i;

		new_csiphy_dev = devm_kzalloc(&pdev->dev,
		sizeof(struct csiphy_device), GFP_KERNEL);
		@@ -183,18 +184,23 @@ static int cam_csiphy_component_bind(struct device *dev,

		platform_set_drvdata(pdev, &(new_csiphy_dev->v4l2_dev_str.sd));

		new_csiphy_dev->bridge_intf.device_hdl[0] = -1;
		new_csiphy_dev->bridge_intf.device_hdl[1] = -1;
		new_csiphy_dev->bridge_intf.ops.get_dev_info =
		NULL;
		new_csiphy_dev->bridge_intf.ops.link_setup =
		NULL;
		new_csiphy_dev->bridge_intf.ops.apply_req =
		NULL;
		for (i = 0; i < CSIPHY_MAX_INSTANCES_PER_PHY; i++) {
		new_csiphy_dev->csiphy_info[i].hdl_data.device_hdl = -1;
		new_csiphy_dev->csiphy_info[i].hdl_data.session_hdl = -1;
		new_csiphy_dev->csiphy_info[i].csiphy_3phase = -1;
		new_csiphy_dev->csiphy_info[i].data_rate = 0;
		new_csiphy_dev->csiphy_info[i].settle_time = 0;
		new_csiphy_dev->csiphy_info[i].lane_cnt = 0;
		new_csiphy_dev->csiphy_info[i].lane_assign = 0;
		new_csiphy_dev->csiphy_info[i].lane_enable = 0;
		}

		new_csiphy_dev->ops.get_dev_info = NULL;
		new_csiphy_dev->ops.link_setup = NULL;
		new_csiphy_dev->ops.apply_req = NULL;

		new_csiphy_dev->acquire_count = 0;
		new_csiphy_dev->start_dev_count = 0;
		new_csiphy_dev->is_acquired_dev_combo_mode = 0;

		cpas_parms.cam_cpas_client_cb = NULL;
		cpas_parms.cell_index = new_csiphy_dev->soc_info.index;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

+81 −73

Original line number	Diff line number	Diff line
		@@ -29,7 +29,7 @@
		#include "cam_context.h"

		#define MAX_CSIPHY 6
		#define MAX_DPHY_DATA_LN 4

		#define MAX_LRME_V4l2_EVENTS 30
		#define CSIPHY_NUM_CLK_MAX 16
		#define MAX_CSIPHY_REG_ARRAY 70
		@@ -41,6 +41,7 @@
		#define MAX_DATA_RATE_REGS 30

		#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"
		#define CAM_CSIPHY_RX_CLK_SRC "cphy_rx_src_clk"

		#define CSIPHY_POWER_UP 0
		#define CSIPHY_POWER_DOWN 1
		@@ -53,19 +54,24 @@
		#define CSIPHY_2PH_REGS 5
		#define CSIPHY_3PH_REGS 6

		#define CSIPHY_MAX_INSTANCES 2
		#define CSIPHY_MAX_INSTANCES_PER_PHY 3

		#define CAM_CSIPHY_MAX_DPHY_LANES 4
		#define CAM_CSIPHY_MAX_CPHY_LANES 3
		#define CAM_CSIPHY_MAX_CPHY_DPHY_COMBO_LN 3
		#define CAM_CSIPHY_MAX_CPHY_COMBO_LN 3

		#define ENABLE_IRQ false

		#undef CDBG
		#ifdef CAM_CSIPHY_CORE_DEBUG
		#define CDBG(fmt, args...) pr_err(fmt, ##args)
		#else
		#define CDBG(fmt, args...) pr_debug(fmt, ##args)
		#endif
		#define DPHY_LANE_0 BIT(0)
		#define CPHY_LANE_0 BIT(1)
		#define DPHY_LANE_1 BIT(2)
		#define CPHY_LANE_1 BIT(3)
		#define DPHY_LANE_2 BIT(4)
		#define CPHY_LANE_2 BIT(5)
		#define DPHY_LANE_3 BIT(6)
		#define DPHY_CLK_LN BIT(7)

		#define ENABLE_IRQ false

		enum cam_csiphy_state {
		CAM_CSIPHY_INIT,
		@@ -111,6 +117,7 @@ struct csiphy_reg_parms_t {
		uint32_t csiphy_reset_array_size;
		uint32_t csiphy_2ph_config_array_size;
		uint32_t csiphy_3ph_config_array_size;
		uint32_t csiphy_2ph_3ph_config_array_size;
		uint32_t csiphy_cpas_cp_bits_per_phy;
		uint32_t csiphy_cpas_cp_is_interleaved;
		uint32_t csiphy_cpas_cp_2ph_offset;
		@@ -123,15 +130,10 @@ struct csiphy_reg_parms_t {
		* struct csiphy_intf_params
		* @device_hdl: Device Handle
		* @session_hdl: Session Handle
		* @ops: KMD operations
		* @crm_cb: Callback API pointers
		*/
		struct csiphy_intf_params {
		int32_t device_hdl[CSIPHY_MAX_INSTANCES];
		int32_t session_hdl[CSIPHY_MAX_INSTANCES];
		int32_t link_hdl[CSIPHY_MAX_INSTANCES];
		struct cam_req_mgr_kmd_ops ops;
		struct cam_req_mgr_crm_cb *crm_cb;
		struct csiphy_hdl_tbl {
		int32_t device_hdl;
		int32_t session_hdl;
		};

		/**
		@@ -200,38 +202,35 @@ struct csiphy_ctrl_t {
		struct csiphy_reg_t (*csiphy_2ph_reg)[MAX_SETTINGS_PER_LANE];
		struct csiphy_reg_t (*csiphy_2ph_combo_mode_reg)[MAX_SETTINGS_PER_LANE];
		struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];
		struct csiphy_reg_t (*csiphy_3ph_combo_reg)[MAX_SETTINGS_PER_LANE];
		struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE];
		enum cam_vote_level (getclockvoting)(struct csiphy_device phy_dev);
		enum cam_vote_level (getclockvoting)(struct csiphy_device phy_dev,
		int32_t index);
		struct data_rate_settings_t *data_rates_settings_table;
		};

		/**
		* cam_csiphy_param: Provides cmdbuffer structre
		* @lane_mask : Lane mask details
		* cam_csiphy_param : Provides cmdbuffer structure
		* @lane_assign : Lane sensor will be using
		* @csiphy_3phase : Mentions DPHY or CPHY
		* @combo_mode : Info regarding combo_mode is enable / disable
		* @lane_cnt : Total number of lanes
		* @reserved
		* @3phase : Details whether 3Phase / 2Phase operation
		* @secure_mode : To identify whether stream is secure/nonsecure
		* @lane_enable : Data Lane selection
		* @settle_time : Settling time in ms
		* @settle_time_combo_sensor : Settling time in ms
		* @data_rate : Data rate in mbps
		* @data_rate_combo_sensor: data rate of combo sensor
		* in the the same phy
		*
		* @csiphy_3phase : To identify DPHY or CPHY
		* @csiphy_cpas_cp_reg_mask : CP reg mask for phy instance
		* @hdl_data : CSIPHY handle table
		*/
		struct cam_csiphy_param {
		uint16_t lane_mask;
		uint16_t lane_assign;
		uint8_t csiphy_3phase;
		uint8_t combo_mode;
		uint8_t lane_cnt;
		uint8_t secure_mode[CSIPHY_MAX_INSTANCES];
		uint8_t secure_mode;
		uint32_t lane_enable;
		uint64_t settle_time;
		uint64_t settle_time_combo_sensor;
		uint64_t data_rate;
		uint64_t data_rate_combo_sensor;
		int csiphy_3phase;
		uint64_t csiphy_cpas_cp_reg_mask;
		struct csiphy_hdl_tbl hdl_data;
		};

		/**
		@@ -255,14 +254,17 @@ struct cam_csiphy_param {
		* @csi_3phase: Is it a 3Phase mode
		* @ref_count: Reference count
		* @clk_lane: Clock lane
		* @rx_clk_src_idx: Phy src clk index
		* @acquire_count: Acquire device count
		* @start_dev_count: Start count
		* @is_acquired_dev_combo_mode: Flag that mentions whether already acquired
		* device is for combo mode
		* @soc_info: SOC information
		* @cpas_handle: CPAS handle
		* @config_count: Config reg count
		* @csiphy_cpas_cp_reg_mask: CP reg mask for phy instance
		* @current_data_rate: Data rate in mbps
		* @csiphy_3phase: To identify DPHY or CPHY at top level
		* @combo_mode: Info regarding combo_mode is enable / disable
		* @ops: KMD operations
		* @crm_cb: Callback API pointers
		*/
		struct csiphy_device {
		char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
		@@ -273,23 +275,29 @@ struct csiphy_device {
		uint32_t csiphy_max_clk;
		struct msm_cam_clk_info csiphy_3p_clk_info[2];
		struct clk *csiphy_3p_clk[2];
		unsigned char csi_3phase;
		int32_t ref_count;
		uint16_t lane_mask[MAX_CSIPHY];
		uint8_t is_csiphy_3phase_hw;
		uint8_t is_divisor_32_comp;
		uint8_t num_irq_registers;
		struct cam_subdev v4l2_dev_str;
		struct cam_csiphy_param csiphy_info;
		struct csiphy_intf_params bridge_intf;
		struct cam_csiphy_param csiphy_info[
		CSIPHY_MAX_INSTANCES_PER_PHY];
		uint32_t clk_lane;
		uint8_t rx_clk_src_idx;
		uint32_t acquire_count;
		uint32_t start_dev_count;
		uint32_t is_acquired_dev_combo_mode;
		struct cam_hw_soc_info soc_info;
		uint32_t cpas_handle;
		uint32_t config_count;
		uint64_t csiphy_cpas_cp_reg_mask[CSIPHY_MAX_INSTANCES];
		uint64_t current_data_rate;
		uint64_t csiphy_cpas_cp_reg_mask[
		CSIPHY_MAX_INSTANCES_PER_PHY];
		uint8_t session_max_device_support;
		uint8_t combo_mode;
		uint8_t cphy_dphy_combo_mode;
		struct cam_req_mgr_kmd_ops ops;
		struct cam_req_mgr_crm_cb *crm_cb;
		};

		/**

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

+19 −14

Original line number	Diff line number	Diff line
		@@ -126,26 +126,25 @@ int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev)



		enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev)
		enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev,
		int32_t index)
		{
		CAM_DBG(CAM_CSIPHY, "voting for SVS");
		return CAM_SVS_VOTE;
		}

		enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)
		enum cam_vote_level get_clk_voting_dynamic(
		struct csiphy_device *csiphy_dev, int32_t index)
		{
		uint32_t cam_vote_level = 0;
		uint32_t last_valid_vote = 0;
		struct cam_hw_soc_info *soc_info;
		uint64_t phy_data_rate = csiphy_dev->csiphy_info.data_rate;
		uint64_t phy_data_rate = csiphy_dev->csiphy_info[index].data_rate;

		soc_info = &csiphy_dev->soc_info;
		phy_data_rate = max(phy_data_rate, csiphy_dev->current_data_rate);

		if (csiphy_dev->is_acquired_dev_combo_mode)
		phy_data_rate = max(phy_data_rate,
		csiphy_dev->csiphy_info.data_rate_combo_sensor);

		if (csiphy_dev->csiphy_info.csiphy_3phase) {
		if (csiphy_dev->csiphy_info[index].csiphy_3phase) {
		if (csiphy_dev->is_divisor_32_comp)
		do_div(phy_data_rate, CSIPHY_DIVISOR_32);
		else
		@@ -156,19 +155,21 @@ enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)

		/* round off to next integer */
		phy_data_rate += 1;
		csiphy_dev->current_data_rate = phy_data_rate;

		for (cam_vote_level = 0;
		cam_vote_level < CAM_MAX_VOTE; cam_vote_level++) {
		if (soc_info->clk_level_valid[cam_vote_level] != true)
		continue;

		if (soc_info->clk_rate[cam_vote_level][0] >
		phy_data_rate) {
		if (soc_info->clk_rate[cam_vote_level]
		[csiphy_dev->rx_clk_src_idx] > phy_data_rate) {
		CAM_DBG(CAM_CSIPHY,
		"match detected %s : %llu:%d level : %d",
		soc_info->clk_name[0],
		soc_info->clk_name[csiphy_dev->rx_clk_src_idx],
		phy_data_rate,
		soc_info->clk_rate[cam_vote_level][0],
		soc_info->clk_rate[cam_vote_level]
		[csiphy_dev->rx_clk_src_idx],
		cam_vote_level);
		return cam_vote_level;
		}
		@@ -177,7 +178,7 @@ enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)
		return last_valid_vote;
		}

		int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev)
		int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev, int32_t index)
		{
		int32_t rc = 0;
		struct cam_hw_soc_info *soc_info;
		@@ -191,7 +192,7 @@ int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev)
		return rc;
		}

		vote_level = csiphy_dev->ctrl_reg->getclockvoting(csiphy_dev);
		vote_level = csiphy_dev->ctrl_reg->getclockvoting(csiphy_dev, index);
		rc = cam_soc_util_enable_platform_resource(soc_info, true,
		vote_level, ENABLE_IRQ);
		if (rc < 0) {
		@@ -486,6 +487,10 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
		csiphy_dev->csiphy_3p_clk[1] =
		soc_info->clk[i];
		continue;
		} else if (!strcmp(soc_info->clk_name[i],
		CAM_CSIPHY_RX_CLK_SRC)) {
		csiphy_dev->rx_clk_src_idx = i;
		continue;
		}

		CAM_DBG(CAM_CSIPHY, "clk_rate[%d] = %d", clk_cnt,

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h

+1 −4

Original line number	Diff line number	Diff line
		@@ -21,9 +21,6 @@
		#include "cam_csiphy_dev.h"
		#include "cam_csiphy_core.h"

		#undef CDBG
		#define CDBG(fmt, args...) pr_debug(fmt, ##args)

		#define CSI_3PHASE_HW 1
		#define CSIPHY_VERSION_V35 0x35
		#define CSIPHY_VERSION_V10 0x10
		@@ -56,7 +53,7 @@ int cam_csiphy_parse_dt_info(struct platform_device *pdev,
		*
		* This API enables SOC related parameters
		*/
		int cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev);
		int cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev, int32_t index);

		/**
		* @csiphy_dev: CSIPhy device structure