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Commit e3c839b1 authored by Santosh Mardi's avatar Santosh Mardi Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add DCVS nodes for shima target 

Add DCVS nodes to scale L3, LLCC and DDR based on the traffic
for shima target.

Change-Id: I129119f4ffb4b1c897ef2281eacab8ef21be05d2
parent 52f57a24

qcom/shima.dtsi

+523 −0
Original line number Diff line number Diff line
@@ -15,6 +15,14 @@ 
#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>



#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\

				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\

				opp-supported-hw = <ddrtype>;}

#define DDR_TYPE_LPDDR4X	7

#define DDR_TYPE_LPDDR5		8



/ {

	model = "Qualcomm Technologies, Inc. Shima";

	compatible = "qcom,shima";
@@ -1737,6 +1745,521 @@ 
		status = "disabled";

	};



	llcc_pmu: llcc-pmu@9095000 {

		compatible = "qcom,llcc-pmu-ver2";

		reg = <0x09095000 0x300>;

		reg-names = "lagg-base";

	};



	llcc_bw_opp_table: llcc-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(  150, 32); /*  4576 MB/s */

		BW_OPP_ENTRY(  300, 32); /*  9154 MB/s */

		BW_OPP_ENTRY(  466, 32); /* 14220 MB/s */

		BW_OPP_ENTRY(  600, 32); /* 18310 MB/s */

		BW_OPP_ENTRY(  806, 32); /* 24596 MB/s */

		BW_OPP_ENTRY(  933, 32); /* 28472 MB/s */

		BW_OPP_ENTRY( 1066, 32); /* 30516 MB/s */

	};



	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY_DDR(  200, 4, 0x180); /*   762 MB/s */

		BW_OPP_ENTRY_DDR(  451, 4, 0x180); /*  1720 MB/s */

		BW_OPP_ENTRY_DDR(  547, 4, 0x180); /*  2086 MB/s */

		BW_OPP_ENTRY_DDR(  768, 4, 0x180); /*  2929 MB/s */

		BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /*  3879 MB/s */

		BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /*  5931 MB/s */

		BW_OPP_ENTRY_DDR( 1708, 4, 0x180); /*  6515 MB/s */

		BW_OPP_ENTRY_DDR( 2092, 4, 0x100); /*  7980 MB/s */

		BW_OPP_ENTRY_DDR( 2133, 4,  0x80); /*  8136 MB/s */

		BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */

		BW_OPP_ENTRY_DDR( 3196, 4, 0x100); /* 12191 MB/s */

	};



	qoslat_opp_table: qoslat-opp-table {

		compatible = "operating-points-v2";

		opp-1 {

			opp-hz = /bits/ 64 < 1 >;

		};



		opp-2 {

			opp-hz = /bits/ 64 < 2 >;

		};

	};



	cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {

		compatible = "qcom,devfreq-icc";

		governor = "bw_hwmon";

		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x90b6400 0x300>, <0x90b6300 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&cpu_cpu_llcc_bw>;

		qcom,count-unit = <0x10000>;

	};



	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {

		compatible = "qcom,devfreq-icc-ddr";

		governor = "bw_hwmon";

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {

		compatible = "qcom,bimc-bwmon5";

		reg = <0x9091000 0x1000>;

		reg-names = "base";

		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&cpu_llcc_ddr_bw>;

		qcom,count-unit = <0x10000>;

	};



	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU0>;

	};



	cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU1>;

	};



	cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU2>;

	};



	cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU3>;

	};



	cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU4>;

	};



	cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU5>;

	};



	cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU6>;

	};



	cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		governor = "mem_latency";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_CPU7>;

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devfreq-icc";

		governor = "mem_latency";

		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {

		compatible = "qcom,devfreq-icc";

		governor = "mem_latency";

		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devfreq-icc-ddr";

		governor = "mem_latency";

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {

		compatible = "qcom,devfreq-icc-ddr";

		governor = "mem_latency";

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {

		compatible = "qcom,devfreq-icc-ddr";

		governor = "compute";

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {

		compatible = "qcom,devfreq-icc-ddr";

		governor = "compute";

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor {

		compatible = "qcom,devfreq-icc";

		governor = "compute";

		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {

		compatible = "qcom,devfreq-icc-ddr";

		governor = "compute";

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {

		compatible = "qcom,devfreq-qoslat";

		governor = "mem_latency";

		operating-points-v2 = <&qoslat_opp_table>;

		mboxes = <&qmp_aop 0>;

	};



	cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {

		qcom,core-dev-table =

			<  300000  300000000 >,

			<  691200  556800000 >,

			<  940800  652800000 >,

			< 1171200  844800000 >,

			< 1516800 1065600000 >,

			< 1670400 1305600000 >,

			< 1804800 1420800000 >;

	};



	cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl {

		qcom,core-dev-table =

			<  940800  556800000 >,

			< 1209600  806400000 >,

			< 1651200 1190400000 >,

			< 1900800 1401600000 >,

			< 2361600 1420800000 >;

	};



	cpu7_cpu_l3_tbl: qcom,cpu7-cpu-l3-tbl {

		qcom,core-dev-table =

			< 1094400  556800000 >,

			< 1267200  806400000 >,

			< 1766400 1190400000 >,

			< 2227200 1401600000 >,

			< 2707200 1420800000 >;

	};



	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;



		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0>;

			qcom,target-dev = <&cpu0_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;

		};



		cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU1>;

			qcom,target-dev = <&cpu1_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;

		};



		cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU2>;

			qcom,target-dev = <&cpu2_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;

		};



		cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU3>;

			qcom,target-dev = <&cpu3_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;

		};



		cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4>;

			qcom,target-dev = <&cpu4_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,access-ev = <0x2B>;

			qcom,wb-ev = <0x18>;

			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;

		};



		cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU5>;

			qcom,target-dev = <&cpu5_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,access-ev = <0x2B>;

			qcom,wb-ev = <0x18>;

			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;

		};



		cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6>;

			qcom,target-dev = <&cpu6_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,access-ev = <0x2B>;

			qcom,wb-ev = <0x18>;

			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;

		};



		cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU7>;

			qcom,target-dev = <&cpu7_cpu_l3_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,access-ev = <0x2B>;

			qcom,wb-ev = <0x18>;

			qcom,core-dev-table = <&cpu7_cpu_l3_tbl>;

		};



		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,target-dev = <&cpu0_cpu_llcc_lat>;

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				< 1171200 MHZ_TO_MBPS( 300, 32) >,

				< 1516800 MHZ_TO_MBPS( 466, 32) >,

				< 1804800 MHZ_TO_MBPS( 600, 32) >;

		};



		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x1000>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					<  691200 MHZ_TO_MBPS(  300, 4) >,

					<  940800 MHZ_TO_MBPS(  451, 4) >,

					< 1171200 MHZ_TO_MBPS(  547, 4) >,

					< 1516800 MHZ_TO_MBPS(  768, 4) >,

					< 1804800 MHZ_TO_MBPS( 1017, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					<  691200 MHZ_TO_MBPS(  300, 4) >,

					<  940800 MHZ_TO_MBPS(  451, 4) >,

					< 1171200 MHZ_TO_MBPS(  547, 4) >,

					< 1516800 MHZ_TO_MBPS(  768, 4) >,

					< 1804800 MHZ_TO_MBPS( 1555, 4) >;

			};

		};



		cpu0_computemon: qcom,cpu0-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

			qcom,core-dev-table =

					<  691000 MHZ_TO_MBPS( 200, 4) >,

					< 1171200 MHZ_TO_MBPS( 451, 4) >,

					< 1516800 MHZ_TO_MBPS( 547, 4) >,

					< 1804800 MHZ_TO_MBPS( 768, 4) >;

		};



		cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,target-dev = <&cpu4_cpu_llcc_lat>;

			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				<  691000 MHZ_TO_MBPS(  300, 32) >,

				<  940800 MHZ_TO_MBPS(  466, 32) >,

				< 1209600 MHZ_TO_MBPS(  600, 32) >,

				< 1651800 MHZ_TO_MBPS(  806, 32) >,

				< 2361600 MHZ_TO_MBPS(  933, 32) >,

				< 2707200 MHZ_TO_MBPS( 1066, 32) >;

		};



		cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6>;

			qcom,target-dev = <&cpu4_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x1000>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					<  691000 MHZ_TO_MBPS( 451, 4) >,

					<  940800 MHZ_TO_MBPS( 547, 4) >,

					< 1209600 MHZ_TO_MBPS(1017, 4) >,

					< 1651800 MHZ_TO_MBPS(1555, 4) >,

					< 2361600 MHZ_TO_MBPS(1708, 4) >,

					< 2707200 MHZ_TO_MBPS(2133, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					<  691000 MHZ_TO_MBPS( 451, 4) >,

					<  940800 MHZ_TO_MBPS( 547, 4) >,

					< 1209600 MHZ_TO_MBPS(1017, 4) >,

					< 1651800 MHZ_TO_MBPS(1555, 4) >,

					< 1900800 MHZ_TO_MBPS(1708, 4) >,

					< 2361600 MHZ_TO_MBPS(2092, 4) >,

					< 2707200 MHZ_TO_MBPS(3196, 4) >;

			};

		};



		cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU7>;

			qcom,target-dev = <&cpu4_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x1000>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					<  2361600 MHZ_TO_MBPS( 300, 4) >,

					<  2707200 MHZ_TO_MBPS(2133, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					<  2361600 MHZ_TO_MBPS( 300, 4) >,

					<  2707200 MHZ_TO_MBPS(3196, 4) >;

			};

		};



		cpu4_computemon: qcom,cpu4-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;

			qcom,cpulist = <&CPU4 &CPU5 &CPU6>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					<  691000 MHZ_TO_MBPS( 451, 4) >,

					< 1209600 MHZ_TO_MBPS( 547, 4) >,

					< 1497600 MHZ_TO_MBPS( 768, 4) >,

					< 1651800 MHZ_TO_MBPS(1017, 4) >,

					< 1900800 MHZ_TO_MBPS(1555, 4) >,

					< 2361600 MHZ_TO_MBPS(1708, 4) >,

					< 2707200 MHZ_TO_MBPS(2133, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					<  691000 MHZ_TO_MBPS( 451, 4) >,

					< 1209600 MHZ_TO_MBPS( 547, 4) >,

					< 1497600 MHZ_TO_MBPS( 768, 4) >,

					< 1651800 MHZ_TO_MBPS(1017, 4) >,

					< 1900800 MHZ_TO_MBPS(1708, 4) >,

					< 2361600 MHZ_TO_MBPS(2092, 4) >,

					< 2707200 MHZ_TO_MBPS(3196, 4) >;

			};

		};



		cpu4_llcc_computemon: qcom,cpu4-llcc-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;

			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			qcom,core-dev-table =

				< 1900800 MHZ_TO_MBPS( 150, 32) >,

				< 2707200 MHZ_TO_MBPS( 600, 32) >;

		};



		cpu7_computemon: qcom,cpu7-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;

			qcom,cpulist = <&CPU7>;

			ddr4-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR4X>;

				qcom,core-dev-table =

					< 2361600 MHZ_TO_MBPS( 300, 4) >,

					< 2707200 MHZ_TO_MBPS(2033, 4) >;

			};



			ddr5-map {

				qcom,ddr-type = <DDR_TYPE_LPDDR5>;

				qcom,core-dev-table =

					< 2361600 MHZ_TO_MBPS( 300, 4) >,

					< 2707200 MHZ_TO_MBPS(3196, 4) >;

			};

		};



		cpu4_qoslatmon: qcom,cpu4-qoslatmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;

			qcom,cachemiss-ev = <0x1000>;

			qcom,core-dev-table =

				<  300000 1 >,

				< 3000000 2 >;

		};

	};



	qcom,sps {

		compatible = "qcom,msm-sps-4k";

		qcom,pipe-attr-ee;