Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e376df94 authored by Yoshihiro Kaneko's avatar Yoshihiro Kaneko Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a774c0: Sort nodes



Sort nodes.

If node address is present
   * Sort by node address, grouping all nodes with the same compat string
     and sorting the group alphabetically.
Else
   * Sort alphabetically

This should not have any run-time effect.

Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 63a0f811
Loading
Loading
Loading
Loading
+45 −45
Original line number Diff line number Diff line
@@ -1371,6 +1371,17 @@
				      "ssi.1", "ssi.0";
			status = "disabled";

			rcar_sound,ctu {
				ctu00: ctu-0 { };
				ctu01: ctu-1 { };
				ctu02: ctu-2 { };
				ctu03: ctu-3 { };
				ctu10: ctu-4 { };
				ctu11: ctu-5 { };
				ctu12: ctu-6 { };
				ctu13: ctu-7 { };
			};

			rcar_sound,dvc {
				dvc0: dvc-0 {
					dmas = <&audma0 0xbc>;
@@ -1387,17 +1398,6 @@
				mix1: mix-1 { };
			};

			rcar_sound,ctu {
				ctu00: ctu-0 { };
				ctu01: ctu-1 { };
				ctu02: ctu-2 { };
				ctu03: ctu-3 { };
				ctu10: ctu-4 { };
				ctu11: ctu-5 { };
				ctu12: ctu-6 { };
				ctu13: ctu-7 { };
			};

			rcar_sound,src {
				src0: src-0 {
					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -1706,13 +1706,24 @@
			renesas,fcp = <&fcpvb0>;
		};

		fcpvb0: fcp@fe96f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfe96f000 0 0x200>;
			clocks = <&cpg CPG_MOD 607>;
		vspd0: vsp@fea20000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea20000 0 0x7000>;
			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 623>;
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 607>;
			iommus = <&ipmmu_vp0 5>;
			resets = <&cpg 623>;
			renesas,fcp = <&fcpvd0>;
		};

		vspd1: vsp@fea28000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea28000 0 0x7000>;
			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 622>;
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 622>;
			renesas,fcp = <&fcpvd1>;
		};

		vspi0: vsp@fe9a0000 {
@@ -1725,23 +1736,13 @@
			renesas,fcp = <&fcpvi0>;
		};

		fcpvi0: fcp@fe9af000 {
		fcpvb0: fcp@fe96f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfe9af000 0 0x200>;
			clocks = <&cpg CPG_MOD 611>;
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 611>;
			iommus = <&ipmmu_vp0 8>;
		};

		vspd0: vsp@fea20000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea20000 0 0x7000>;
			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 623>;
			reg = <0 0xfe96f000 0 0x200>;
			clocks = <&cpg CPG_MOD 607>;
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 623>;
			renesas,fcp = <&fcpvd0>;
			resets = <&cpg 607>;
			iommus = <&ipmmu_vp0 5>;
		};

		fcpvd0: fcp@fea27000 {
@@ -1753,16 +1754,6 @@
			iommus = <&ipmmu_vi0 8>;
		};

		vspd1: vsp@fea28000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea28000 0 0x7000>;
			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 622>;
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 622>;
			renesas,fcp = <&fcpvd1>;
		};

		fcpvd1: fcp@fea2f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfea2f000 0 0x200>;
@@ -1772,6 +1763,15 @@
			iommus = <&ipmmu_vi0 9>;
		};

		fcpvi0: fcp@fe9af000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfe9af000 0 0x200>;
			clocks = <&cpg CPG_MOD 611>;
			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
			resets = <&cpg 611>;
			iommus = <&ipmmu_vp0 8>;
		};

		csi40: csi2@feaa0000 {
			compatible = "renesas,r8a774c0-csi2";
			reg = <0 0xfeaa0000 0 0x10000>;
@@ -1908,6 +1908,9 @@
			polling-delay = <1000>;
			thermal-sensors = <&thermal>;

			cooling-maps {
			};

			trips {
				cpu-crit {
					temperature = <120000>;
@@ -1915,9 +1918,6 @@
					type = "critical";
				};
			};

			cooling-maps {
			};
		};
	};