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Commit e2cdf640 authored by Ken Wang's avatar Ken Wang Committed by Alex Deucher
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drm/amdgpu: add display controller implementation for si v10 



v4: rebase fixups
v5: more fixes based on dce8 code
v6: squash in dmif offset fix
v7: rebase fixups
v8: rebase fixups, drop some debugging remnants
v9: fix BE build
v10: include Marek's tiling fixes, add support for
     page_flip_target, set MASTER_UDPATE_MODE=0,
     fix cursor

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarKen Wang <Qingqing.Wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 27ae1064

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

0 → 100644
+3160 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/dce_v6_0.h

0 → 100644
+29 −0
Original line number Original line Diff line number Diff line 
/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __DCE_V6_0_H__

#define __DCE_V6_0_H__



extern const struct amd_ip_funcs dce_v6_0_ip_funcs;



#endif

drivers/gpu/drm/amd/include/asic_reg/si/sid.h

+4 −33
Original line number Original line Diff line number Diff line
@@ -1976,9 +1976,6 @@ 
#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 << 20)

#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1            (2 << 20)

#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 << 20)

#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1            (4 << 20)





#define AMDGPU_TILING_MACRO				0x1

#define AMDGPU_TILING_MICRO				0x2



#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1a45

#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1a45

#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1845

#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH                0x1845
@@ -2119,35 +2116,9 @@ 
#define EVERGREEN_GRPH_SWAP_CONTROL                     0x1a03

#define EVERGREEN_GRPH_SWAP_CONTROL                     0x1a03

#define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)

#define EVERGREEN_GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)

#       define EVERGREEN_GRPH_ENDIAN_NONE               0

#       define EVERGREEN_GRPH_ENDIAN_NONE               0



#       define EVERGREEN_GRPH_ENDIAN_8IN16              1

/* this object requires a surface when mapped - i.e. front buffer */

#       define EVERGREEN_GRPH_ENDIAN_8IN32              2

#define RADEON_TILING_SURFACE				0x10

#       define EVERGREEN_GRPH_ENDIAN_8IN64              3

#define RADEON_TILING_MICRO_SQUARE			0x20

#define RADEON_TILING_EG_BANKW_SHIFT			8

#define RADEON_TILING_EG_BANKW_MASK			0xf

#define RADEON_TILING_EG_BANKH_SHIFT			12

#define RADEON_TILING_EG_BANKH_MASK			0xf

#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT	16

#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK		0xf

#define RADEON_TILING_EG_TILE_SPLIT_SHIFT		24

#define RADEON_TILING_EG_TILE_SPLIT_MASK		0xf

#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT	28

#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf



#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED	8

#define SI_TILE_MODE_COLOR_1D			13

#define SI_TILE_MODE_COLOR_1D_SCANOUT		9

#define SI_TILE_MODE_COLOR_2D_8BPP		14

#define SI_TILE_MODE_COLOR_2D_16BPP		15

#define SI_TILE_MODE_COLOR_2D_32BPP		16

#define SI_TILE_MODE_COLOR_2D_64BPP		17

#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP	11

#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP	12

#define SI_TILE_MODE_DEPTH_STENCIL_1D		4

#define SI_TILE_MODE_DEPTH_STENCIL_2D		0

#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA	3

#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3

#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2





#define EVERGREEN_D3VGA_CONTROL                         0xf8

#define EVERGREEN_D3VGA_CONTROL                         0xf8

#define EVERGREEN_D4VGA_CONTROL                         0xf9

#define EVERGREEN_D4VGA_CONTROL                         0xf9