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Commit e2b2175e authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: add support for 3DP 4K@120Hz on vega10. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cf2f0a37

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c

+80 −8
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#include "cgs_common.h"

#include "vega10_pptable.h"



#define NUM_DSPCLK_LEVELS 8



static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,

		enum phm_platform_caps cap)

{
@@ -644,11 +646,11 @@ static int get_gfxclk_voltage_dependency_table( 
	return 0;

}



static int get_dcefclk_voltage_dependency_table(

static int get_pix_clk_voltage_dependency_table(

		struct pp_hwmgr *hwmgr,

		struct phm_ppt_v1_clock_voltage_dependency_table

			**pp_vega10_clk_dep_table,

		const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)

		const  ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)

{

	uint32_t table_size, i;

	struct phm_ppt_v1_clock_voltage_dependency_table
@@ -681,6 +683,76 @@ static int get_dcefclk_voltage_dependency_table( 
	return 0;

}



static int get_dcefclk_voltage_dependency_table(

		struct pp_hwmgr *hwmgr,

		struct phm_ppt_v1_clock_voltage_dependency_table

			**pp_vega10_clk_dep_table,

		const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)

{

	uint32_t table_size, i;

	uint8_t num_entries;

	struct phm_ppt_v1_clock_voltage_dependency_table

				*clk_table;

	struct cgs_system_info sys_info = {0};

	uint32_t dev_id;

	uint32_t rev_id;



	PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),

			"Invalid PowerPlay Table!", return -1);



/*

 * workaround needed to add another DPM level for pioneer cards

 * as VBIOS is locked down.

 * This DPM level was added to support 3DPM monitors @ 4K120Hz

 *

 */

	sys_info.size = sizeof(struct cgs_system_info);

	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_DEV;

	cgs_query_system_info(hwmgr->device, &sys_info);

	dev_id = (uint32_t)sys_info.value;



	sys_info.size = sizeof(struct cgs_system_info);

	sys_info.info_id = CGS_SYSTEM_INFO_PCIE_REV;

	cgs_query_system_info(hwmgr->device, &sys_info);

	rev_id = (uint32_t)sys_info.value;



	if (dev_id == 0x6863 && rev_id == 0 &&

		clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)

		num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ?

				NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1;

	else

		num_entries = clk_dep_table->ucNumEntries;





	table_size = sizeof(uint32_t) +

			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *

			num_entries;



	clk_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)

			kzalloc(table_size, GFP_KERNEL);



	if (!clk_table)

		return -ENOMEM;



	clk_table->count = (uint32_t)num_entries;



	for (i = 0; i < clk_dep_table->ucNumEntries; i++) {

		clk_table->entries[i].vddInd =

				clk_dep_table->entries[i].ucVddInd;

		clk_table->entries[i].clk =

				le32_to_cpu(clk_dep_table->entries[i].ulClk);

	}



	if (i < num_entries) {

		clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd;

		clk_table->entries[i].clk = 90000;

	}



	*pp_vega10_clk_dep_table = clk_table;



	return 0;

}



static int get_pcie_table(struct pp_hwmgr *hwmgr,

		struct phm_ppt_v1_pcie_table **vega10_pcie_table,

		const Vega10_PPTable_Generic_SubTable_Header *table)
@@ -862,21 +934,21 @@ static int init_powerplay_extended_tables( 
				gfxclk_dep_table);



	if (!result && powerplay_table->usPixclkDependencyTableOffset)

		result = get_dcefclk_voltage_dependency_table(hwmgr,

		result = get_pix_clk_voltage_dependency_table(hwmgr,

				&pp_table_info->vdd_dep_on_pixclk,

				(const ATOM_Vega10_DCEFCLK_Dependency_Table*)

				(const ATOM_Vega10_PIXCLK_Dependency_Table*)

				pixclk_dep_table);



	if (!result && powerplay_table->usPhyClkDependencyTableOffset)

		result = get_dcefclk_voltage_dependency_table(hwmgr,

		result = get_pix_clk_voltage_dependency_table(hwmgr,

				&pp_table_info->vdd_dep_on_phyclk,

				(const ATOM_Vega10_DCEFCLK_Dependency_Table *)

				(const ATOM_Vega10_PIXCLK_Dependency_Table *)

				phyclk_dep_table);



	if (!result && powerplay_table->usDispClkDependencyTableOffset)

		result = get_dcefclk_voltage_dependency_table(hwmgr,

		result = get_pix_clk_voltage_dependency_table(hwmgr,

				&pp_table_info->vdd_dep_on_dispclk,

				(const ATOM_Vega10_DCEFCLK_Dependency_Table *)

				(const ATOM_Vega10_PIXCLK_Dependency_Table *)

				dispclk_dep_table);



	if (!result && powerplay_table->usDcefclkDependencyTableOffset)