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Commit e2921f9f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-07-26' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Daniel Vetter:
 "Dave seems to collect an entire streak of things happening, so again
  me typing pull summary.

  Nothing nefarious here, most of the fixes are for new stuff or things
  users won't see. The amd-display patches are a bit different, and very
  much look like they should have at least some cc: stable tags. Might
  be amd is a bit too comfortable with their internal tree and not
  enough looking at upstream. Dave&me are looking into this, in case
  something needs rectified with process here.

  Also no intel fixes pull, but intel CI is general become rather good,
  still I guess expect a notch more for -rc3.

  Summary:

  amdgpu:
   - fixes for (new in 5.3) hw support (vega20, navi)
   - disable RAS
   - lots of display fixes all over (audio, DSC, dongle, clock mgr)

  ttm:
   - fix dma_free_attrs calls to appease dma debugging

  msm:
   - fixes for dma-api, locking debug and compiler splats

  core:
   - fix cmdline mode to not apply rotation if not specified (new in 5.3)
   - compiler warn fix"

* tag 'drm-fixes-2019-07-26' of git://anongit.freedesktop.org/drm/drm: (46 commits)
  drm/amd/display: Set enabled to false at start of audio disable
  drm/amdgpu/smu: move fan rpm query into the asic specific code
  drm/amd/powerplay: custom peak clock freq for navi10
  drm: silence variable 'conn' set but not used
  drm/msm: stop abusing dma_map/unmap for cache
  drm/msm/dpu: Correct dpu encoder spinlock initialization
  drm/msm: correct NULL pointer dereference in context_init
  drm/amd/display: handle active dongle port type is DP++ or DP case
  drm/amd/display: do not read link setting if edp not connected
  drm/amd/display: Increase size of audios array
  drm/amd/display: drop ASSERT() if eDP panel is not connected
  drm/amd/display: Only enable audio if speaker allocation exists
  drm/amd/display: Fix dc_create failure handling and 666 color depths
  drm/amd/display: allocate 4 ddc engines for RV2
  drm/amd/display: put back front end initialization sequence
  drm/amd/display: Wait for flip to complete
  drm/amd/display: Change min_h_sync_width from 8 to 4
  drm/amd/display: use encoder's engine id to find matched free audio device
  drm/amd/display: fix DMCU hang when going into Modern Standby
  drm/amd/display: Disable Audio on reinitialize hardware
  ...
parents 3ea54d9b 4d5308e7

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+1 −1
Original line number Diff line number Diff line
@@ -148,7 +148,7 @@ struct amdgpu_mgpu_info mgpu_info = { 
	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),

};

int amdgpu_ras_enable = -1;

uint amdgpu_ras_mask = 0xffffffff;

uint amdgpu_ras_mask = 0xfffffffb;



/**

 * DOC: vramlimit (int)

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+2 −2
Original line number Diff line number Diff line
@@ -1734,7 +1734,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 
		return -EINVAL;



	if (is_support_sw_smu(adev)) {

		err = smu_get_current_rpm(&adev->smu, &speed);

		err = smu_get_fan_speed_rpm(&adev->smu, &speed);

		if (err)

			return err;

	} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
@@ -1794,7 +1794,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 
		return -EINVAL;



	if (is_support_sw_smu(adev)) {

		err = smu_get_current_rpm(&adev->smu, &rpm);

		err = smu_get_fan_speed_rpm(&adev->smu, &rpm);

		if (err)

			return err;

	} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+12 −7
Original line number Diff line number Diff line
@@ -136,11 +136,6 @@ static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev, 
static int amdgpu_ras_release_vram(struct amdgpu_device *adev,

		struct amdgpu_bo **bo_ptr);



static void amdgpu_ras_self_test(struct amdgpu_device *adev)

{

	/* TODO */

}



static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,

					size_t size, loff_t *pos)

{
@@ -689,6 +684,12 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, 
	if (!obj)

		return -EINVAL;



	if (block_info.block_id != TA_RAS_BLOCK__UMC) {

		DRM_INFO("%s error injection is not supported yet\n",

			 ras_block_str(info->head.block));

		return -EINVAL;

	}



	ret = psp_ras_trigger_error(&adev->psp, &block_info);

	if (ret)

		DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
@@ -1557,6 +1558,12 @@ int amdgpu_ras_init(struct amdgpu_device *adev) 


	amdgpu_ras_check_supported(adev, &con->hw_supported,

			&con->supported);

	if (!con->hw_supported) {

		amdgpu_ras_set_context(adev, NULL);

		kfree(con);

		return 0;

	}



	con->features = 0;

	INIT_LIST_HEAD(&con->head);

	/* Might need get this flag from vbios. */
@@ -1570,8 +1577,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev) 
	if (amdgpu_ras_fs_init(adev))

		goto fs_out;



	amdgpu_ras_self_test(adev);



	DRM_INFO("RAS INFO: ras initialized successfully, "

			"hardware ability[%x] ras_mask[%x]\n",

			con->hw_supported, con->supported);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+9 −0
Original line number Diff line number Diff line
@@ -1441,6 +1441,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 
	}

	nv_grbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);



	/* Initialize all compute VMIDs to have no GDS, GWS, or OA

	   acccess. These should be enabled by FW for target VMIDs. */

	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);

		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);

	}

}



static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+9 −0
Original line number Diff line number Diff line
@@ -1879,6 +1879,15 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 
	}

	cik_srbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);



	/* Initialize all compute VMIDs to have no GDS, GWS, or OA

	   acccess. These should be enabled by FW for target VMIDs. */

	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {

		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);

		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);

		WREG32(amdgpu_gds_reg_offset[i].gws, 0);

		WREG32(amdgpu_gds_reg_offset[i].oa, 0);

	}

}



static void gfx_v7_0_config_init(struct amdgpu_device *adev)