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Commit e2516652 authored by Doug Brown's avatar Doug Brown Committed by Greg Kroah-Hartman
Browse files

ARM: mmp: fix timer_read delay 



[ Upstream commit e348b4014c31041e13ff370669ba3348c4d385e3 ]

timer_read() was using an empty 100-iteration loop to wait for the
TMR_CVWR register to capture the latest timer counter value. The delay
wasn't long enough. This resulted in CPU idle time being extremely
underreported on PXA168 with CONFIG_NO_HZ_IDLE=y.

Switch to the approach used in the vendor kernel, which implements the
capture delay by reading TMR_CVWR a few times instead.

Fixes: 49cbe786 ("[ARM] pxa: add base support for Marvell's PXA168 processor line")
Signed-off-by: default avatarDoug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20221204005117.53452-3-doug@schmorgal.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 2de791ff

arch/arm/mach-mmp/time.c

+7 −4
Original line number Diff line number Diff line
@@ -44,18 +44,21 @@ 
static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;



/*

 * FIXME: the timer needs some delay to stablize the counter capture

 * Read the timer through the CVWR register. Delay is required after requesting

 * a read. The CR register cannot be directly read due to metastability issues

 * documented in the PXA168 software manual.

 */

static inline uint32_t timer_read(void)

{

	int delay = 100;

	uint32_t val;

	int delay = 3;



	__raw_writel(1, mmp_timer_base + TMR_CVWR(1));



	while (delay--)

		cpu_relax();

		val = __raw_readl(mmp_timer_base + TMR_CVWR(1));



	return __raw_readl(mmp_timer_base + TMR_CVWR(1));

	return val;

}



static u64 notrace mmp_read_sched_clock(void)