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Commit e244ff6f authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Geert Uytterhoeven
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pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions 



This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 100431b6

drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c

+75 −22
Original line number Diff line number Diff line
@@ -537,6 +537,9 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ 
	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \

	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)



#define PINMUX_PHYS \

	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)



enum {

	PINMUX_RESERVED = 0,
@@ -562,6 +565,7 @@ enum { 
	PINMUX_IPSR

	PINMUX_MOD_SELS

	PINMUX_STATIC

	PINMUX_PHYS

	PINMUX_MARK_END,

#undef F_

#undef FM
@@ -574,9 +578,6 @@ static const u16 pinmux_data[] = { 
	PINMUX_SINGLE(AVS2),

	PINMUX_SINGLE(HDMI0_CEC),

	PINMUX_SINGLE(HDMI1_CEC),

	PINMUX_SINGLE(I2C_SEL_0_1),

	PINMUX_SINGLE(I2C_SEL_3_1),

	PINMUX_SINGLE(I2C_SEL_5_1),

	PINMUX_SINGLE(MSIOF0_RXD),

	PINMUX_SINGLE(MSIOF0_SCK),

	PINMUX_SINGLE(MSIOF0_TXD),
@@ -608,13 +609,15 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),

	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),



	PINMUX_IPSR_MSEL(IP0_19_16,	AVB_AVTP_MATCH_A,	SEL_ETHERAVB_0),

	PINMUX_IPSR_MSEL(IP0_19_16,	MSIOF2_RXD_C,		SEL_MSIOF2_2),

	PINMUX_IPSR_MSEL(IP0_19_16,	CTS4_N_A,		SEL_SCIF4_0),

	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),

	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),

	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),

	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),



	PINMUX_IPSR_MSEL(IP0_23_20,	AVB_AVTP_CAPTURE_A,	SEL_ETHERAVB_0),

	PINMUX_IPSR_MSEL(IP0_23_20,	MSIOF2_TXD_C,		SEL_MSIOF2_2),

	PINMUX_IPSR_MSEL(IP0_23_20,	RTS4_N_TANS_A,		SEL_SCIF4_0),

	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),

	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),

	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A,		I2C_SEL_5_0,	SEL_SCIF4_0),

	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),



	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),

	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
@@ -664,16 +667,18 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),

	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),



	PINMUX_IPSR_MSEL(IP1_23_20,	PWM1_A,			SEL_PWM1_0),

	PINMUX_IPSR_GPSR(IP1_23_20,	A21),

	PINMUX_IPSR_MSEL(IP1_23_20,	HRX3_D,			SEL_HSCIF3_3),

	PINMUX_IPSR_MSEL(IP1_23_20,	VI4_DATA7_B,		SEL_VIN4_1),

	PINMUX_IPSR_MSEL(IP1_23_20,	IERX_B,			SEL_IEBUS_1),

	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),

	PINMUX_IPSR_MSEL(IP1_23_20,	A21,			I2C_SEL_3_0),

	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),

	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),

	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),

	PINMUX_IPSR_PHYS(IP0_23_20,	SCL3,			I2C_SEL_3_1),



	PINMUX_IPSR_MSEL(IP1_27_24,	PWM2_A,			SEL_PWM2_0),

	PINMUX_IPSR_GPSR(IP1_27_24,	A20),

	PINMUX_IPSR_MSEL(IP1_27_24,	HTX3_D,			SEL_HSCIF3_3),

	PINMUX_IPSR_MSEL(IP1_27_24,	IETX_B,			SEL_IEBUS_1),

	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),

	PINMUX_IPSR_MSEL(IP1_27_24,	A20,			I2C_SEL_3_0),

	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),

	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),

	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),



	PINMUX_IPSR_GPSR(IP1_31_28,	A0),

	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
@@ -1067,11 +1072,13 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_GPSR(IP10_15_12,	SD0_WP),

	PINMUX_IPSR_MSEL(IP10_15_12,	SDA2_B,			SEL_I2C2_1),



	PINMUX_IPSR_GPSR(IP10_19_16,	SD1_CD),

	PINMUX_IPSR_MSEL(IP10_19_16,	SIM0_CLK_B,		SEL_SIMCARD_1),

	PINMUX_IPSR_MSEL(IP10_19_16,	SD1_CD,			I2C_SEL_0_0),

	PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),

	PINMUX_IPSR_PHYS(IP10_19_16,	SCL0,			I2C_SEL_0_1),



	PINMUX_IPSR_GPSR(IP10_23_20,	SD1_WP),

	PINMUX_IPSR_MSEL(IP10_23_20,	SIM0_D_B,		SEL_SIMCARD_1),

	PINMUX_IPSR_MSEL(IP10_23_20,	SD1_WP,			I2C_SEL_0_0),

	PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),

	PINMUX_IPSR_PHYS(IP10_23_20,	SDA0,			I2C_SEL_0_1),



	PINMUX_IPSR_GPSR(IP10_27_24,	SCK0),

	PINMUX_IPSR_MSEL(IP10_27_24,	HSCK1_B,		SEL_HSCIF1_1),
@@ -2266,6 +2273,15 @@ static const unsigned int hscif4_data_b_mux[] = { 
};



/* - I2C -------------------------------------------------------------------- */

static const unsigned int i2c0_pins[] = {

	/* SCL, SDA */

	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),

};



static const unsigned int i2c0_mux[] = {

	SCL0_MARK, SDA0_MARK,

};



static const unsigned int i2c1_a_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
@@ -2294,6 +2310,25 @@ static const unsigned int i2c2_b_pins[] = { 
static const unsigned int i2c2_b_mux[] = {

	SDA2_B_MARK, SCL2_B_MARK,

};



static const unsigned int i2c3_pins[] = {

	/* SCL, SDA */

	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),

};



static const unsigned int i2c3_mux[] = {

	SCL3_MARK, SDA3_MARK,

};



static const unsigned int i2c5_pins[] = {

	/* SCL, SDA */

	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),

};



static const unsigned int i2c5_mux[] = {

	SCL5_MARK, SDA5_MARK,

};



static const unsigned int i2c6_a_pins[] = {

	/* SDA, SCL */

	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
@@ -3936,10 +3971,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(hscif4_clk),

	SH_PFC_PIN_GROUP(hscif4_ctrl),

	SH_PFC_PIN_GROUP(hscif4_data_b),

	SH_PFC_PIN_GROUP(i2c0),

	SH_PFC_PIN_GROUP(i2c1_a),

	SH_PFC_PIN_GROUP(i2c1_b),

	SH_PFC_PIN_GROUP(i2c2_a),

	SH_PFC_PIN_GROUP(i2c2_b),

	SH_PFC_PIN_GROUP(i2c3),

	SH_PFC_PIN_GROUP(i2c5),

	SH_PFC_PIN_GROUP(i2c6_a),

	SH_PFC_PIN_GROUP(i2c6_b),

	SH_PFC_PIN_GROUP(i2c6_c),
@@ -4309,6 +4347,10 @@ static const char * const hscif4_groups[] = { 
	"hscif4_data_b",

};



static const char * const i2c0_groups[] = {

	"i2c0",

};



static const char * const i2c1_groups[] = {

	"i2c1_a",

	"i2c1_b",
@@ -4319,6 +4361,14 @@ static const char * const i2c2_groups[] = { 
	"i2c2_b",

};



static const char * const i2c3_groups[] = {

	"i2c3",

};



static const char * const i2c5_groups[] = {

	"i2c5",

};



static const char * const i2c6_groups[] = {

	"i2c6_a",

	"i2c6_b",
@@ -4651,8 +4701,11 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(hscif2),

	SH_PFC_FUNCTION(hscif3),

	SH_PFC_FUNCTION(hscif4),

	SH_PFC_FUNCTION(i2c0),

	SH_PFC_FUNCTION(i2c1),

	SH_PFC_FUNCTION(i2c2),

	SH_PFC_FUNCTION(i2c3),

	SH_PFC_FUNCTION(i2c5),

	SH_PFC_FUNCTION(i2c6),

	SH_PFC_FUNCTION(intc_ex),

	SH_PFC_FUNCTION(msiof0),