Commit e1a50de3 authored Feb 16, 2018 by Robin Murphy Committed by Catalin Marinas Feb 17, 2018

arm64: cputype: Silence Sparse warnings



Sparse makes a fair bit of noise about our MPIDR mask being implicitly
long - let's explicitly describe it as such rather than just relying on
the value forcing automatic promotion.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

parent 20a004e7

arch/arm64/include/asm/cputype.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -20,7 +20,7 @@

		#define MPIDR_UP_BITMASK (0x1 << 30)
		#define MPIDR_MT_BITMASK (0x1 << 24)
		#define MPIDR_HWID_BITMASK 0xff00ffffff
		#define MPIDR_HWID_BITMASK 0xff00ffffffUL

		#define MPIDR_LEVEL_BITS_SHIFT 3
		#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)