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Commit e1547c53 authored by Jes Sorensen's avatar Jes Sorensen Committed by Kalle Valo
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rtl8xxxu: First stab at adding IQK calibration for 8723bu parts 



The 8723bu also has it's own IQK calibration process. This is similar
in flow, but still different enough to warrent it's own
implementation, at least for now.

Signed-off-by: default avatarJes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent c6594ffd

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

+809 −2

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h

+1 −0
Original line number Diff line number Diff line
@@ -851,6 +851,7 @@ struct rtl8xxxu_fileops { 
	int (*power_on) (struct rtl8xxxu_priv *priv);

	int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page);

	void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);

	void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);

	int writeN_block_size;

	u16 mbox_ext_reg;

	char mbox_ext_width;

drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h

+17 −0
Original line number Diff line number Diff line
@@ -708,6 +708,12 @@ 
#define REG_MACID1			0x0700

#define REG_BSSID1			0x0708



/*

 * This seems to be 8723bu specific

 */

#define REG_BT_CONTROL_8723BU		0x0764

#define  BT_CONTROL_BT_GRANT		BIT(12)



#define REG_FPGA0_RF_MODE		0x0800

#define  FPGA_RF_MODE			BIT(0)

#define  FPGA_RF_MODE_JAPAN		BIT(1)
@@ -810,6 +816,7 @@ 
#define REG_RFE_CTRL_ANTA_SRC		0x0930	/* 8723BU */

#define REG_RFE_PATH_SELECT		0x0940	/* 8723BU */

#define REG_RFE_BUFFER			0x0944	/* 8723BU */

#define REG_S0S1_PATH_SWITCH		0x0948	/* 8723BU */



#define REG_CCK0_SYSTEM			0x0a00

#define  CCK0_SIDEBAND			BIT(4)
@@ -1050,3 +1057,13 @@ 
#define RF6052_REG_TXPA_G1		0x31	/* RF TX PA control */

#define RF6052_REG_TXPA_G2		0x32	/* RF TX PA control */

#define RF6052_REG_TXPA_G3		0x33	/* RF TX PA control */



/*

 * NextGen regs: 8723BU

 */

#define	RF6052_REG_UNKNOWN_43		0x43

#define	RF6052_REG_UNKNOWN_55		0x55

#define	RF6052_REG_S0S1			0xb0

#define	RF6052_REG_UNKNOWN_DF		0xdf

#define	RF6052_REG_UNKNOWN_ED		0xed

#define	RF6052_REG_WE_LUT		0xef