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Commit e13c6d14 authored by Vinod Koul's avatar Vinod Koul Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8150: Add base dts file 



This add base DTS file with cpu, psci, firmware, clock node tlmm and
spmi and enables boot to console

Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Reviewed-by: default avatarNiklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent b4d08173

arch/arm64/boot/dts/qcom/sm8150.dtsi

0 → 100644
+308 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019, Linaro Limited

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/clock/qcom,rpmh.h>



/ {

	interrupt-parent = <&intc>;



	#address-cells = <2>;

	#size-cells = <2>;



	chosen { };



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <38400000>;

			clock-output-names = "xo_board";

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32764>;

			clock-output-names = "sleep_clk";

		};

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

				L3_0: l3-cache {

				      compatible = "cache";

				};

			};

		};



		CPU1: cpu@100 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			L2_100: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};



		};



		CPU2: cpu@200 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x200>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			L2_200: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU3: cpu@300 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x300>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			L2_300: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU4: cpu@400 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x400>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			L2_400: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU5: cpu@500 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x500>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			L2_500: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU6: cpu@600 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x600>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			L2_600: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};



		CPU7: cpu@700 {

			device_type = "cpu";

			compatible = "qcom,kryo485";

			reg = <0x0 0x700>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			L2_700: l2-cache {

				compatible = "cache";

				next-level-cache = <&L3_0>;

			};

		};

	};



	firmware {

		scm: scm {

			compatible = "qcom,scm-sm8150", "qcom,scm";

			#reset-cells = <1>;

		};

	};



	memory@80000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0x0 0x80000000 0x0 0x0>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	soc: soc@0 {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges = <0 0 0 0 0x10 0>;

		dma-ranges = <0 0 0 0 0x10 0>;

		compatible = "simple-bus";



		gcc: clock-controller@100000 {

			compatible = "qcom,gcc-sm8150";

			reg = <0x0 0x00100000 0x0 0x1f0000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

			clock-names = "bi_tcxo",

				      "sleep_clk";

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&sleep_clk>;

		};



		qupv3_id_1: geniqup@ac0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0x0 0x00ac0000 0x0 0x6000>;

			clock-names = "m-ahb", "s-ahb";

			clocks = <&gcc 123>,

				 <&gcc 124>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			status = "disabled";



			uart2: serial@a90000 {

				compatible = "qcom,geni-debug-uart";

				reg = <0x0 0x00a90000 0x0 0x4000>;

				clock-names = "se";

				clocks = <&gcc 105>;

				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};

		};



		tlmm: pinctrl@3100000 {

			compatible = "qcom,sm8150-pinctrl";

			reg = <0x0 0x03100000 0x0 0x300000>,

			      <0x0 0x03500000 0x0 0x300000>,

			      <0x0 0x03900000 0x0 0x300000>,

			      <0x0 0x03D00000 0x0 0x300000>;

			reg-names = "west", "east", "north", "south";

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-ranges = <&tlmm 0 0 175>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		spmi_bus: spmi@c440000 {

			compatible = "qcom,spmi-pmic-arb";

			reg = <0x0 0x0c440000 0x0 0x0001100>,

			      <0x0 0x0c600000 0x0 0x2000000>,

			      <0x0 0x0e600000 0x0 0x0100000>,

			      <0x0 0x0e700000 0x0 0x00a0000>,

			      <0x0 0x0c40a000 0x0 0x0026000>;

			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

			interrupt-names = "periph_irq";

			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ee = <0>;

			qcom,channel = <0>;

			#address-cells = <2>;

			#size-cells = <0>;

			interrupt-controller;

			#interrupt-cells = <4>;

			cell-index = <0>;

		};



		intc: interrupt-controller@17a00000 {

			compatible = "arm,gic-v3";

			interrupt-controller;

			#interrupt-cells = <3>;

			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */

			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		timer@17c20000 {

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0x0 0x17c20000 0x0 0x1000>;

			clock-frequency = <19200000>;



			frame@17c21000{

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c21000 0x0 0x1000>,

				      <0x0 0x17c22000 0x0 0x1000>;

			};



			frame@17c23000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c23000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17c25000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c25000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17c27000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c26000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17c29000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c29000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17c2b000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c2b000 0x0 0x1000>;

				status = "disabled";

			};



			frame@17c2d000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0 0x17c2d000 0x0 0x1000>;

				status = "disabled";

			};

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;

	};

};