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Commit e1236bc0 authored by Changbin Du's avatar Changbin Du Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Align render mmio list to cacheline 



Make the global mmio list be cacheline aligned to improve performance.

Signed-off-by: default avatarChangbin Du <changbin.du@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 0b063bd3

drivers/gpu/drm/i915/gvt/render.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -44,7 +44,7 @@ struct render_mmio { 
	u32 value;

	u32 value;

};

};





static struct render_mmio gen8_render_mmio_list[] = {

static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = {

	{RCS, _MMIO(0x229c), 0xffff, false},

	{RCS, _MMIO(0x229c), 0xffff, false},

	{RCS, _MMIO(0x2248), 0x0, false},

	{RCS, _MMIO(0x2248), 0x0, false},

	{RCS, _MMIO(0x2098), 0x0, false},

	{RCS, _MMIO(0x2098), 0x0, false},
@@ -75,7 +75,7 @@ static struct render_mmio gen8_render_mmio_list[] = { 
	{BCS, _MMIO(0x22028), 0x0, false},

	{BCS, _MMIO(0x22028), 0x0, false},

};

};





static struct render_mmio gen9_render_mmio_list[] = {

static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = {

	{RCS, _MMIO(0x229c), 0xffff, false},

	{RCS, _MMIO(0x229c), 0xffff, false},

	{RCS, _MMIO(0x2248), 0x0, false},

	{RCS, _MMIO(0x2248), 0x0, false},

	{RCS, _MMIO(0x2098), 0x0, false},

	{RCS, _MMIO(0x2098), 0x0, false},