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Commit e1012141 authored by Julien Masson's avatar Julien Masson Committed by Neil Armstrong
Browse files

drm: meson: global clean-up 



This patch aims to:
- Add general and TODO comments
- Respect coding style for multi-line comments
- Align macro definitions
- Remove useless macro

Signed-off-by: default avatarJulien Masson <jmasson@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86pnn382e8.fsf@baylibre.com
parent 7eef9e61

drivers/gpu/drm/meson/meson_dw_hdmi.c

+2 −0
Original line number Diff line number Diff line
@@ -429,6 +429,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 
	/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */

	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,

			       0x3, 0x3);



	/* Enable cec_clk and hdcp22_tmdsclk_en */

	dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,

			       0x3 << 4, 0x3 << 4);

drivers/gpu/drm/meson/meson_dw_hdmi.h

+8 −4
Original line number Diff line number Diff line
@@ -100,7 +100,8 @@ 
#define HDMITX_TOP_INTR_RXSENSE_RISE	BIT(6)

#define HDMITX_TOP_INTR_RXSENSE_FALL	BIT(7)



/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;

/*

 * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;

 *     3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.

 * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern

 *     every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
@@ -135,7 +136,8 @@ 
/* Bit  9: 0 RW tmds_clk_pttn[29:20]. Default 0. */

#define HDMITX_TOP_TMDS_CLK_PTTN_23             (0x00B)



/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,

/*

 * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,

 * used when TMDS CLK rate = TMDS character rate /4. Default 0.

 * Bit 0 R  Reserved. Default 0.

 * [	1] shift_tmds_clk_pttn
@@ -143,12 +145,14 @@ 
 */

#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL           (0x00C)



/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM

/*

 * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM

 * failure, write 1 to clear the failure flag.  Default 0.

 */

#define HDMITX_TOP_REVOCMEM_STAT                (0x00D)



/* Bit	   1 R	filtered RxSense status

/*

 * Bit	   1 R	filtered RxSense status

 * Bit     0 R  filtered HPD status.

 */

#define HDMITX_TOP_STAT0                        (0x00E)

drivers/gpu/drm/meson/meson_registers.h

+14 −17
Original line number Diff line number Diff line
@@ -621,6 +621,7 @@ 
#define OSD34_SCI_WH_M1 0x3d29

#define OSD34_SCO_H_START_END 0x3d2a

#define OSD34_SCO_V_START_END 0x3d2b



/* viu2 */

#define VIU2_ADDR_START 0x1e00

#define VIU2_ADDR_END 0x1eff
@@ -1603,7 +1604,6 @@ 
#define OSD1_AFBCD_STATUS 0x31a8

#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9

#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa

#define VIU_MISC_CTRL1 0x1a07



/* add for gxm and 962e dv core2 */

#define DOLBY_CORE2A_SWAP_CTRL1	0x3434
@@ -1618,8 +1618,6 @@ 
#define VPU_MAFBC_COMMAND 0x3a05

#define VPU_MAFBC_STATUS 0x3a06

#define VPU_MAFBC_SURFACE_CFG 0x3a07



/* osd afbc on g12a */

#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10

#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11

#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12
@@ -1740,6 +1738,5 @@ 
#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969

#define VPP_RDARB_MODE 0x3978

#define VPP_RDARB_REQEN_SLV 0x3979

#define VPU_RDARB_MODE_L2C1 0x279d



#endif /* __MESON_REGISTERS_H */

drivers/gpu/drm/meson/meson_vclk.c

+3 −1
Original line number Diff line number Diff line
@@ -496,6 +496,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, 
		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);



		/* Enable and reset */

		/* TODO: add specific macro for g12a here */

		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,

				   0x3 << 28, 0x3 << 28);
@@ -970,7 +971,8 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, 
		meson_venci_cvbs_clock_config(priv);

		return;

	} else if (target == MESON_VCLK_TARGET_DMT) {

		/* The DMT clock path is fixed after the PLL:

		/*

		 * The DMT clock path is fixed after the PLL:

		 * - automatic PLL freq + OD management

		 * - vid_pll_div = VID_PLL_DIV_5

		 * - vclk_div = 2

drivers/gpu/drm/meson/meson_venc.c

+6 −4
Original line number Diff line number Diff line
@@ -61,9 +61,9 @@ 
/* HHI Registers */

#define HHI_GCLK_MPEG2		0x148 /* 0x52 offset in data sheet */

#define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbd offset in data sheet */

#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbb offset in data sheet */

#define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */

#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbe offset in data sheet */

#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbc offset in data sheet */

#define HHI_HDMI_PHY_CNTL0	0x3a0 /* 0xe8 offset in data sheet */



struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
@@ -1085,7 +1085,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, 
		writel_relaxed(vmode->enci.video_mode,

				priv->io_base + _REG(ENCI_VIDEO_MODE));



		/* Advanced Video Mode :

		/*

		 * Advanced Video Mode :

		 * Demux shifting 0x2

		 * Blank line end at line17/22

		 * High bandwidth Luma Filter
@@ -1599,7 +1600,8 @@ void meson_venci_cvbs_mode_set(struct meson_drm *priv, 
	writel_relaxed(mode->video_mode,

			priv->io_base + _REG(ENCI_VIDEO_MODE));



	/* Advanced Video Mode :

	/*

	 * Advanced Video Mode :

	 * Demux shifting 0x2

	 * Blank line end at line17/22

	 * High bandwidth Luma Filter