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Commit e0f0273e authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Use named initializers for gmch wm params 



Using names initializers when filling out the watermark structs
saves you from having go look up the struct definition every
single time.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ef0cf27c

drivers/gpu/drm/i915/intel_pm.c

+65 −65
Original line number Diff line number Diff line
@@ -865,95 +865,95 @@ static int i845_get_fifo_size(struct drm_device *dev, int plane) 


/* Pineview has different values for various configs */

static const struct intel_watermark_params pineview_display_wm = {

	PINEVIEW_DISPLAY_FIFO,

	PINEVIEW_MAX_WM,

	PINEVIEW_DFT_WM,

	PINEVIEW_GUARD_WM,

	PINEVIEW_FIFO_LINE_SIZE

	.fifo_size = PINEVIEW_DISPLAY_FIFO,

	.max_wm = PINEVIEW_MAX_WM,

	.default_wm = PINEVIEW_DFT_WM,

	.guard_size = PINEVIEW_GUARD_WM,

	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params pineview_display_hplloff_wm = {

	PINEVIEW_DISPLAY_FIFO,

	PINEVIEW_MAX_WM,

	PINEVIEW_DFT_HPLLOFF_WM,

	PINEVIEW_GUARD_WM,

	PINEVIEW_FIFO_LINE_SIZE

	.fifo_size = PINEVIEW_DISPLAY_FIFO,

	.max_wm = PINEVIEW_MAX_WM,

	.default_wm = PINEVIEW_DFT_HPLLOFF_WM,

	.guard_size = PINEVIEW_GUARD_WM,

	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params pineview_cursor_wm = {

	PINEVIEW_CURSOR_FIFO,

	PINEVIEW_CURSOR_MAX_WM,

	PINEVIEW_CURSOR_DFT_WM,

	PINEVIEW_CURSOR_GUARD_WM,

	PINEVIEW_FIFO_LINE_SIZE,

	.fifo_size = PINEVIEW_CURSOR_FIFO,

	.max_wm = PINEVIEW_CURSOR_MAX_WM,

	.default_wm = PINEVIEW_CURSOR_DFT_WM,

	.guard_size = PINEVIEW_CURSOR_GUARD_WM,

	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params pineview_cursor_hplloff_wm = {

	PINEVIEW_CURSOR_FIFO,

	PINEVIEW_CURSOR_MAX_WM,

	PINEVIEW_CURSOR_DFT_WM,

	PINEVIEW_CURSOR_GUARD_WM,

	PINEVIEW_FIFO_LINE_SIZE

	.fifo_size = PINEVIEW_CURSOR_FIFO,

	.max_wm = PINEVIEW_CURSOR_MAX_WM,

	.default_wm = PINEVIEW_CURSOR_DFT_WM,

	.guard_size = PINEVIEW_CURSOR_GUARD_WM,

	.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params g4x_wm_info = {

	G4X_FIFO_SIZE,

	G4X_MAX_WM,

	G4X_MAX_WM,

	2,

	G4X_FIFO_LINE_SIZE,

	.fifo_size = G4X_FIFO_SIZE,

	.max_wm = G4X_MAX_WM,

	.default_wm = G4X_MAX_WM,

	.guard_size = 2,

	.cacheline_size = G4X_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params g4x_cursor_wm_info = {

	I965_CURSOR_FIFO,

	I965_CURSOR_MAX_WM,

	I965_CURSOR_DFT_WM,

	2,

	G4X_FIFO_LINE_SIZE,

	.fifo_size = I965_CURSOR_FIFO,

	.max_wm = I965_CURSOR_MAX_WM,

	.default_wm = I965_CURSOR_DFT_WM,

	.guard_size = 2,

	.cacheline_size = G4X_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params valleyview_wm_info = {

	VALLEYVIEW_FIFO_SIZE,

	VALLEYVIEW_MAX_WM,

	VALLEYVIEW_MAX_WM,

	2,

	G4X_FIFO_LINE_SIZE,

	.fifo_size = VALLEYVIEW_FIFO_SIZE,

	.max_wm = VALLEYVIEW_MAX_WM,

	.default_wm = VALLEYVIEW_MAX_WM,

	.guard_size = 2,

	.cacheline_size = G4X_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params valleyview_cursor_wm_info = {

	I965_CURSOR_FIFO,

	VALLEYVIEW_CURSOR_MAX_WM,

	I965_CURSOR_DFT_WM,

	2,

	G4X_FIFO_LINE_SIZE,

	.fifo_size = I965_CURSOR_FIFO,

	.max_wm = VALLEYVIEW_CURSOR_MAX_WM,

	.default_wm = I965_CURSOR_DFT_WM,

	.guard_size = 2,

	.cacheline_size = G4X_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params i965_cursor_wm_info = {

	I965_CURSOR_FIFO,

	I965_CURSOR_MAX_WM,

	I965_CURSOR_DFT_WM,

	2,

	I915_FIFO_LINE_SIZE,

	.fifo_size = I965_CURSOR_FIFO,

	.max_wm = I965_CURSOR_MAX_WM,

	.default_wm = I965_CURSOR_DFT_WM,

	.guard_size = 2,

	.cacheline_size = I915_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params i945_wm_info = {

	I945_FIFO_SIZE,

	I915_MAX_WM,

	1,

	2,

	I915_FIFO_LINE_SIZE

	.fifo_size = I945_FIFO_SIZE,

	.max_wm = I915_MAX_WM,

	.default_wm = 1,

	.guard_size = 2,

	.cacheline_size = I915_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params i915_wm_info = {

	I915_FIFO_SIZE,

	I915_MAX_WM,

	1,

	2,

	I915_FIFO_LINE_SIZE

	.fifo_size = I915_FIFO_SIZE,

	.max_wm = I915_MAX_WM,

	.default_wm = 1,

	.guard_size = 2,

	.cacheline_size = I915_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params i830_wm_info = {

	I855GM_FIFO_SIZE,

	I915_MAX_WM,

	1,

	2,

	I830_FIFO_LINE_SIZE

	.fifo_size = I855GM_FIFO_SIZE,

	.max_wm = I915_MAX_WM,

	.default_wm = 1,

	.guard_size = 2,

	.cacheline_size = I830_FIFO_LINE_SIZE,

};

static const struct intel_watermark_params i845_wm_info = {

	I830_FIFO_SIZE,

	I915_MAX_WM,

	1,

	2,

	I830_FIFO_LINE_SIZE

	.fifo_size = I830_FIFO_SIZE,

	.max_wm = I915_MAX_WM,

	.default_wm = 1,

	.guard_size = 2,

	.cacheline_size = I830_FIFO_LINE_SIZE,

};



/**