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Commit e0d07657 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
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drm/amdgpu: update golden setting programming logic



Since from soc15, make sure only AndMasked bit get changed
when applied or_mask

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarLe Ma <Le.Ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6bdadb20
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+4 −1
Original line number Diff line number Diff line
@@ -509,6 +509,9 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
		} else {
			tmp = RREG32(reg);
			tmp &= ~and_mask;
			if (adev->family >= AMDGPU_FAMILY_AI)
				tmp |= (or_mask & and_mask);
			else
				tmp |= or_mask;
		}
		WREG32(reg, tmp);
+1 −1
Original line number Diff line number Diff line
@@ -378,7 +378,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
		} else {
			tmp = RREG32(reg);
			tmp &= ~(entry->and_mask);
			tmp |= entry->or_mask;
			tmp |= (entry->or_mask & entry->and_mask);
		}

		if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||