Loading drivers/gpu/msm/adreno.c +27 −5 Original line number Diff line number Diff line Loading @@ -2573,6 +2573,27 @@ int adreno_set_constraint(struct kgsl_device *device, return status; } static void adreno_force_on(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); if (gmu_core_isenabled(device)) { set_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags); if (!adreno_active_count_get(adreno_dev)) adreno_active_count_put(adreno_dev); return; } kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE); device->pwrctrl.ctrl_flags = KGSL_PWR_ON; adreno_fault_detect_stop(adreno_dev); } static int adreno_setproperty(struct kgsl_device_private *dev_priv, unsigned int type, void __user *value, Loading @@ -2597,6 +2618,10 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv, mutex_lock(&device->mutex); if (enable) { if (gmu_core_isenabled(device)) clear_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags); else device->pwrctrl.ctrl_flags = 0; if (!adreno_active_count_get(adreno_dev)) { Loading @@ -2606,10 +2631,7 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv, kgsl_pwrscale_enable(device); } else { kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE); device->pwrctrl.ctrl_flags = KGSL_PWR_ON; adreno_fault_detect_stop(adreno_dev); adreno_force_on(adreno_dev); kgsl_pwrscale_disable(device, true); } Loading drivers/gpu/msm/adreno_a6xx_gmu.c +8 −7 Original line number Diff line number Diff line Loading @@ -2821,25 +2821,21 @@ static int a6xx_gmu_power_off(struct adreno_device *adreno_dev) void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct kgsl_pwrctrl *pwr = &device->pwrctrl; adreno_irqctrl(adreno_dev, 1); enable_irq(pwr->interrupt_num); kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_ON); trace_kgsl_irq(device, 1); adreno_irqctrl(adreno_dev, 1); } void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct kgsl_pwrctrl *pwr = &device->pwrctrl; disable_irq(pwr->interrupt_num); kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); if (a6xx_gmu_gx_is_on(device)) adreno_irqctrl(adreno_dev, 0); trace_kgsl_irq(device, 0); } static int a6xx_gpu_boot(struct adreno_device *adreno_dev) Loading Loading @@ -3112,14 +3108,19 @@ static void gmu_idle_check(struct work_struct *work) mutex_lock(&device->mutex); if (test_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags)) goto done; if (!atomic_read(&device->active_cnt)) { if (test_bit(GMU_PRIV_GPU_STARTED, &gmu->flags)) a6xx_power_off(adreno_dev); } else { kgsl_pwrscale_update(device); mod_timer(&device->idle_timer, jiffies + device->pwrctrl.interval_timeout); } done: mutex_unlock(&device->mutex); } Loading drivers/gpu/msm/adreno_a6xx_rgmu.c +8 −2 Original line number Diff line number Diff line Loading @@ -849,12 +849,18 @@ static void rgmu_idle_check(struct work_struct *work) mutex_lock(&device->mutex); if (!atomic_read(&device->active_cnt)) if (test_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags)) goto done; if (!atomic_read(&device->active_cnt)) { a6xx_power_off(adreno_dev); else } else { kgsl_pwrscale_update(device); mod_timer(&device->idle_timer, jiffies + device->pwrctrl.interval_timeout); } done: mutex_unlock(&device->mutex); } Loading drivers/gpu/msm/kgsl_gmu_core.h +1 −0 Original line number Diff line number Diff line Loading @@ -39,6 +39,7 @@ enum gmu_core_flags { GMU_DCVS_REPLAY, GMU_ENABLED, GMU_RSCC_SLEEP_SEQ_DONE, GMU_DISABLE_SLUMBER, }; /* Loading drivers/gpu/msm/kgsl_iommu.c +6 −1 Original line number Diff line number Diff line Loading @@ -649,7 +649,12 @@ static int kgsl_iommu_fault_handler(struct iommu_domain *domain, * The device mutex must be held to change power state */ mutex_lock(&device->mutex); if (gmu_core_isenabled(device)) kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); else kgsl_pwrctrl_change_state(device, KGSL_STATE_AWARE); mutex_unlock(&device->mutex); } Loading Loading
drivers/gpu/msm/adreno.c +27 −5 Original line number Diff line number Diff line Loading @@ -2573,6 +2573,27 @@ int adreno_set_constraint(struct kgsl_device *device, return status; } static void adreno_force_on(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); if (gmu_core_isenabled(device)) { set_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags); if (!adreno_active_count_get(adreno_dev)) adreno_active_count_put(adreno_dev); return; } kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE); device->pwrctrl.ctrl_flags = KGSL_PWR_ON; adreno_fault_detect_stop(adreno_dev); } static int adreno_setproperty(struct kgsl_device_private *dev_priv, unsigned int type, void __user *value, Loading @@ -2597,6 +2618,10 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv, mutex_lock(&device->mutex); if (enable) { if (gmu_core_isenabled(device)) clear_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags); else device->pwrctrl.ctrl_flags = 0; if (!adreno_active_count_get(adreno_dev)) { Loading @@ -2606,10 +2631,7 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv, kgsl_pwrscale_enable(device); } else { kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE); device->pwrctrl.ctrl_flags = KGSL_PWR_ON; adreno_fault_detect_stop(adreno_dev); adreno_force_on(adreno_dev); kgsl_pwrscale_disable(device, true); } Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +8 −7 Original line number Diff line number Diff line Loading @@ -2821,25 +2821,21 @@ static int a6xx_gmu_power_off(struct adreno_device *adreno_dev) void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct kgsl_pwrctrl *pwr = &device->pwrctrl; adreno_irqctrl(adreno_dev, 1); enable_irq(pwr->interrupt_num); kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_ON); trace_kgsl_irq(device, 1); adreno_irqctrl(adreno_dev, 1); } void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct kgsl_pwrctrl *pwr = &device->pwrctrl; disable_irq(pwr->interrupt_num); kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); if (a6xx_gmu_gx_is_on(device)) adreno_irqctrl(adreno_dev, 0); trace_kgsl_irq(device, 0); } static int a6xx_gpu_boot(struct adreno_device *adreno_dev) Loading Loading @@ -3112,14 +3108,19 @@ static void gmu_idle_check(struct work_struct *work) mutex_lock(&device->mutex); if (test_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags)) goto done; if (!atomic_read(&device->active_cnt)) { if (test_bit(GMU_PRIV_GPU_STARTED, &gmu->flags)) a6xx_power_off(adreno_dev); } else { kgsl_pwrscale_update(device); mod_timer(&device->idle_timer, jiffies + device->pwrctrl.interval_timeout); } done: mutex_unlock(&device->mutex); } Loading
drivers/gpu/msm/adreno_a6xx_rgmu.c +8 −2 Original line number Diff line number Diff line Loading @@ -849,12 +849,18 @@ static void rgmu_idle_check(struct work_struct *work) mutex_lock(&device->mutex); if (!atomic_read(&device->active_cnt)) if (test_bit(GMU_DISABLE_SLUMBER, &device->gmu_core.flags)) goto done; if (!atomic_read(&device->active_cnt)) { a6xx_power_off(adreno_dev); else } else { kgsl_pwrscale_update(device); mod_timer(&device->idle_timer, jiffies + device->pwrctrl.interval_timeout); } done: mutex_unlock(&device->mutex); } Loading
drivers/gpu/msm/kgsl_gmu_core.h +1 −0 Original line number Diff line number Diff line Loading @@ -39,6 +39,7 @@ enum gmu_core_flags { GMU_DCVS_REPLAY, GMU_ENABLED, GMU_RSCC_SLEEP_SEQ_DONE, GMU_DISABLE_SLUMBER, }; /* Loading
drivers/gpu/msm/kgsl_iommu.c +6 −1 Original line number Diff line number Diff line Loading @@ -649,7 +649,12 @@ static int kgsl_iommu_fault_handler(struct iommu_domain *domain, * The device mutex must be held to change power state */ mutex_lock(&device->mutex); if (gmu_core_isenabled(device)) kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); else kgsl_pwrctrl_change_state(device, KGSL_STATE_AWARE); mutex_unlock(&device->mutex); } Loading