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Commit e0100d40 authored by Dave Jiang's avatar Dave Jiang Committed by Vinod Koul
Browse files

dmaengine: ioatdma: add descriptor pre-fetch support for v3.4 



Adding support for new feature on ioatdma 3.4 hardware that provides
descriptor pre-fetching in order to reduce small DMA latencies.

Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 11e31e28

drivers/dma/ioat/dma.c

+12 −0
Original line number Diff line number Diff line
@@ -372,6 +372,7 @@ struct ioat_ring_ent ** 
ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags)

{

	struct ioatdma_chan *ioat_chan = to_ioat_chan(c);

	struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;

	struct ioat_ring_ent **ring;

	int total_descs = 1 << order;

	int i, chunks;
@@ -437,6 +438,17 @@ ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags) 
	}

	ring[i]->hw->next = ring[0]->txd.phys;



	/* setup descriptor pre-fetching for v3.4 */

	if (ioat_dma->cap & IOAT_CAP_DPS) {

		u16 drsctl = IOAT_CHAN_DRSZ_2MB | IOAT_CHAN_DRS_EN;



		if (chunks == 1)

			drsctl |= IOAT_CHAN_DRS_AUTOWRAP;



		writew(drsctl, ioat_chan->reg_base + IOAT_CHAN_DRSCTL_OFFSET);



	}



	return ring;

}

drivers/dma/ioat/init.c

+6 −2
Original line number Diff line number Diff line
@@ -138,10 +138,10 @@ static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma); 
static int ioat_dca_enabled = 1;

module_param(ioat_dca_enabled, int, 0644);

MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");

int ioat_pending_level = 4;

int ioat_pending_level = 7;

module_param(ioat_pending_level, int, 0644);

MODULE_PARM_DESC(ioat_pending_level,

		 "high-water mark for pushing ioat descriptors (default: 4)");

		 "high-water mark for pushing ioat descriptors (default: 7)");

static char ioat_interrupt_style[32] = "msix";

module_param_string(ioat_interrupt_style, ioat_interrupt_style,

		    sizeof(ioat_interrupt_style), 0644);
@@ -1188,6 +1188,10 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) 
	if (err)

		return err;



	if (ioat_dma->cap & IOAT_CAP_DPS)

		writeb(ioat_pending_level + 1,

		       ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET);



	return 0;

}

drivers/dma/ioat/registers.h

+10 −0
Original line number Diff line number Diff line
@@ -84,6 +84,9 @@ 
#define IOAT_CAP_PQ				0x00000200

#define IOAT_CAP_DWBES				0x00002000

#define IOAT_CAP_RAID16SS			0x00020000

#define IOAT_CAP_DPS				0x00800000



#define IOAT_PREFETCH_LIMIT_OFFSET		0x4C	/* CHWPREFLMT */



#define IOAT_CHANNEL_MMIO_SIZE			0x80	/* Each Channel MMIO space is this size */
@@ -243,4 +246,11 @@ 


#define IOAT_CHANERR_MASK_OFFSET		0x2C	/* 32-bit Channel Error Register */



#define IOAT_CHAN_DRSCTL_OFFSET			0xB6

#define IOAT_CHAN_DRSZ_4KB			0x0000

#define IOAT_CHAN_DRSZ_8KB			0x0001

#define IOAT_CHAN_DRSZ_2MB			0x0009

#define IOAT_CHAN_DRS_EN			0x0100

#define IOAT_CHAN_DRS_AUTOWRAP			0x0200



#endif /* _IOAT_REGISTERS_H_ */