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Commit dfc165df authored by Ritesh Harjani's avatar Ritesh Harjani Committed by Gerrit - the friendly Code Review server
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UPSTREAM: mmc: sdhci-msm: Don't enable PWRSAVE_DLL for certain sdhc hosts 



SDHC core with new 14lpp and later tech DLL should not enable
PWRSAVE_DLL since such controller's internal gating cannot meet
following MCLK requirement:
When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK
must be switched on for at-least 1us before DATA starts coming.

Adding support for this requirement.

Change-Id: I0a00ea4deb9d043db501d781860361fcac52a58a
Signed-off-by: default avatarRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: default avatarVeerabhadrarao Badiganti <vbadigan@codeaurora.org>
Reviewed-by: default avatarCan Guo <cang@codeaurora.org>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/1581077075-26011-1-git-send-email-vbadigan@codeaurora.org


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarVeerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: default avatarSarthak Garg <sartgarg@codeaurora.org>
parent d4111cad

drivers/mmc/host/sdhci-msm.c

+15 −3
Original line number Diff line number Diff line
@@ -1184,9 +1184,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) 
		goto out;

	}



	config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);

	/*

	 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.

	 * When MCLK is gated OFF, it is not gated for less than 0.5us

	 * and MCLK must be switched on for at-least 1us before DATA

	 * starts coming. Controllers with 14lpp and later tech DLL cannot

	 * guarantee above requirement. So PWRSAVE_DLL should not be

	 * turned on for host controllers using this DLL.

	 */

	if (!msm_host->use_14lpp_dll_reset) {

		config = readl_relaxed(host->ioaddr +

				msm_offset->core_vendor_spec3);

		config |= CORE_PWRSAVE_DLL;

	writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);

		writel_relaxed(config, host->ioaddr +

				msm_offset->core_vendor_spec3);

	}



	/*

	 * Drain writebuffer to ensure above DLL calibration