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Commit df640759 authored by Govindaraj Rajagopal's avatar Govindaraj Rajagopal
Browse files

ARM: dts: msm: Add video device for shima 

Add video device node for shima.

Change-Id: I2b934e61336802eb5c5998752273fe81a33362b5
parent e3ccfb34

qcom/shima-vidc.dtsi

0 → 100644
+294 −0
Original line number Diff line number Diff line 
&soc {

	msm_vidc0: qcom,vidc0 {

		compatible = "qcom,msm-vidc", "qcom,shima-vidc";

		status = "okay";

		sku-index = <1>;

		reg = <0x0aa00000 0x00100000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



		/* IOMMU Config */

		#address-cells = <1>;

		#size-cells = <1>;



		/* Supply */

		iris-ctl-supply = <&video_cc_mvs0c_gdsc>;

		vcodec-supply = <&video_cc_mvs0_gdsc>;



		/* Clocks */

		clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		clocks = <&gcc GCC_VIDEO_AXI0_CLK>,

			<&videocc VIDEO_CC_MVS0C_CLK>,

			<&videocc VIDEO_CC_MVS0_CLK>;

		qcom,proxy-clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/

		qcom,clock-configs = <0x0 0x1 0x1>;

		qcom,allowed-clock-rates = <240000000 338000000

			364800000>;

		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,

			<&videocc VIDEO_CC_MVS0C_CLK_ARES>;

		reset-names = "video_axi_reset", "video_core_reset";



		qcom,reg-presets = <0xB0088 0x0 0x11>;



		/* Video Firmware ELF image name */

		vidc,firmware-name = "vpu20_2v";



		/* Bus Interconnects */

		interconnect-names = "venus-cnoc", "venus-ddr";

		interconnects = <&gem_noc MASTER_APPSS_PROC

					&config_noc SLAVE_VENUS_CFG>,

				<&mmss_noc MASTER_VIDEO_P0

					&mc_virt SLAVE_EBI1>;

		/* Bus BW range (low, high) for each bus */

		qcom,bus-range-kbps = <1000 1000

					1000 15000000>;



		/* MMUs */

		non_secure_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";

			iommus = <&apps_smmu 0x2900 0x0400>;

			qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			buffer-types = <0xfff>;

			virtual-addr-pool = <0x25800000 0xba800000>;

		};



		secure_non_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_non_pixel";

			iommus = <&apps_smmu 0x2904 0x0400>;

			qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */

			buffer-types = <0x480>;

			virtual-addr-pool = <0x01000000 0x24800000>;

			qcom,secure-context-bank;

		};



		secure_bitstream_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_bitstream";

			iommus = <&apps_smmu 0x2901 0x0404>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */

			buffer-types = <0x241>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};



		secure_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_pixel";

			iommus = <&apps_smmu 0x2903 0x0400>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */

			buffer-types = <0x106>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};

	};



	msm_vidc1: qcom,vidc1 {

		compatible = "qcom,msm-vidc", "qcom,shima-vidc";

		status = "okay";

		sku-index = <2>;

		reg = <0x0aa00000 0x00100000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



		/* IOMMU Config */

		#address-cells = <1>;

		#size-cells = <1>;



		/* Supply */

		iris-ctl-supply = <&video_cc_mvs0c_gdsc>;

		vcodec-supply = <&video_cc_mvs0_gdsc>;



		/* Clocks */

		clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		clocks = <&gcc GCC_VIDEO_AXI0_CLK>,

			<&videocc VIDEO_CC_MVS0C_CLK>,

			<&videocc VIDEO_CC_MVS0_CLK>;

		qcom,proxy-clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/

		qcom,clock-configs = <0x0 0x1 0x1>;

		qcom,allowed-clock-rates = <201600000>;

		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,

			<&videocc VIDEO_CC_MVS0C_CLK_ARES>;

		reset-names = "video_axi_reset", "video_core_reset";



		qcom,reg-presets = <0xB0088 0x0 0x11>;



		/* Video Firmware ELF image name */

		vidc,firmware-name = "vpu20_2v";



		/* Bus Interconnects */

		interconnect-names = "venus-cnoc", "venus-ddr";

		interconnects = <&gem_noc MASTER_APPSS_PROC

					&config_noc SLAVE_VENUS_CFG>,

				<&mmss_noc MASTER_VIDEO_P0

					&mc_virt SLAVE_EBI1>;

		/* Bus BW range (low, high) for each bus */

		qcom,bus-range-kbps = <1000 1000

					1000 15000000>;



		/* MMUs */

		non_secure_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";

			iommus = <&apps_smmu 0x2900 0x0400>;

			qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			buffer-types = <0xfff>;

			virtual-addr-pool = <0x25800000 0xba800000>;

		};



		secure_non_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_non_pixel";

			iommus = <&apps_smmu 0x2904 0x0400>;

			qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */

			buffer-types = <0x480>;

			virtual-addr-pool = <0x01000000 0x24800000>;

			qcom,secure-context-bank;

		};



		secure_bitstream_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_bitstream";

			iommus = <&apps_smmu 0x2901 0x0404>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */

			buffer-types = <0x241>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};



		secure_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_pixel";

			iommus = <&apps_smmu 0x2903 0x0400>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */

			buffer-types = <0x106>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};

	};



	msm_vidc2: qcom,vidc2 {

		compatible = "qcom,msm-vidc", "qcom,shima-vidc";

		status = "okay";

		sku-index = <0>;

		reg = <0x0aa00000 0x00100000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



		/* IOMMU Config */

		#address-cells = <1>;

		#size-cells = <1>;



		/* Supply */

		iris-ctl-supply = <&video_cc_mvs0c_gdsc>;

		vcodec-supply = <&video_cc_mvs0_gdsc>;



		/* Clocks */

		clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		clocks = <&gcc GCC_VIDEO_AXI0_CLK>,

			<&videocc VIDEO_CC_MVS0C_CLK>,

			<&videocc VIDEO_CC_MVS0_CLK>;

		qcom,proxy-clock-names = "gcc_video_axi0",

			"core_clk", "vcodec_clk";

		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/

		qcom,clock-configs = <0x0 0x1 0x1>;

		qcom,allowed-clock-rates = <240000000 338000000

			366000000 444000000>;

		resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,

			<&videocc VIDEO_CC_MVS0C_CLK_ARES>;

		reset-names = "video_axi_reset", "video_core_reset";



		qcom,reg-presets = <0xB0088 0x0 0x11>;



		/* Video Firmware ELF image name */

		vidc,firmware-name = "vpu20_2v";



		/* Bus Interconnects */

		interconnect-names = "venus-cnoc", "venus-ddr";

		interconnects = <&gem_noc MASTER_APPSS_PROC

					&config_noc SLAVE_VENUS_CFG>,

				<&mmss_noc MASTER_VIDEO_P0

					&mc_virt SLAVE_EBI1>;

		/* Bus BW range (low, high) for each bus */

		qcom,bus-range-kbps = <1000 1000

					1000 15000000>;



		/* MMUs */

		non_secure_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";

			iommus = <&apps_smmu 0x2900 0x0400>;

			qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			buffer-types = <0xfff>;

			virtual-addr-pool = <0x25800000 0xba800000>;

		};



		secure_non_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_non_pixel";

			iommus = <&apps_smmu 0x2904 0x0400>;

			qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */

			buffer-types = <0x480>;

			virtual-addr-pool = <0x01000000 0x24800000>;

			qcom,secure-context-bank;

		};



		secure_bitstream_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_bitstream";

			iommus = <&apps_smmu 0x2901 0x0404>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */

			buffer-types = <0x241>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};



		secure_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_pixel";

			iommus = <&apps_smmu 0x2903 0x0400>;

			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;

			qcom,iommu-faults = "non-fatal";

			qcom,iommu-pagetable = "LLC";

			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */

			buffer-types = <0x106>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};

	};

};

qcom/shima.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1491,6 +1491,7 @@ 
#include "shima-usb.dtsi"

#include "ipcc-test-shima.dtsi"

#include "msm-arm-smmu-shima.dtsi"

#include "shima-vidc.dtsi"



&gcc_pcie_0_gdsc {

	status = "ok";