Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Unverified Commit df22692b authored by Michael Bestas's avatar Michael Bestas
Browse files

Merge tag 'LA.UM.9.14.r1-19600.01-LAHAINA.QSSI12.0' of... 

Merge tag 'LA.UM.9.14.r1-19600.01-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers into android12-5.4-lahaina

"LA.UM.9.14.r1-19600.01-LAHAINA.QSSI12.0"

* tag 'LA.UM.9.14.r1-19600.01-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers:
  disp: msm: avoid minidump region addition for mdss register dumps
  disp: msm: dsi: avoid setting ulp load to disable load
  disp: msm: dsi: handle read cmd tx failure from dsi host transfer
  disp: msm: sde: unset and set clk parents during pm_suspend
  disp: msm: dsi: handle panel detection after a pp done timeout
  disp: msm: dsi: Fix DMA window scheduling programming

Change-Id: Iebd52dc842fa23e119b15d3d4f1df73f311c48b3
parents 3c398f63 6104617f

techpack/display/msm/dsi/dsi_catalog.c

+2 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/errno.h>
@@ -66,6 +66,7 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, 
		dsi_ctrl_hw_cmn_wait4dynamic_refresh_done;

	ctrl->ops.hs_req_sel = dsi_ctrl_hw_cmn_hs_req_sel;

	ctrl->ops.vid_engine_busy = dsi_ctrl_hw_cmn_vid_engine_busy;

	ctrl->ops.init_cmddma_trig_ctrl = dsi_ctrl_hw_cmn_init_cmddma_trig_ctrl;



	switch (version) {

	case DSI_CTRL_VERSION_1_4:

techpack/display/msm/dsi/dsi_catalog.h

+3 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DSI_CATALOG_H_
@@ -214,6 +214,8 @@ void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en); 
u32 dsi_ctrl_hw_cmn_get_error_mask(struct dsi_ctrl_hw *ctrl);

u32 dsi_ctrl_hw_cmn_get_hw_version(struct dsi_ctrl_hw *ctrl);

int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl);

void dsi_ctrl_hw_cmn_init_cmddma_trig_ctrl(struct dsi_ctrl_hw *ctrl,

					   struct dsi_host_common_cfg *cfg);



/* Definitions specific to 1.4 DSI controller hardware */

int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes);

techpack/display/msm/dsi/dsi_ctrl.c

+5 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/of_device.h>
@@ -1356,6 +1357,10 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl, 
		dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,

				&dsi_ctrl->host_config.common_config);



	if (dsi_hw_ops.init_cmddma_trig_ctrl)

		dsi_hw_ops.init_cmddma_trig_ctrl(&dsi_ctrl->hw,

				&dsi_ctrl->host_config.common_config);



	/*

	 * Always enable DMA scheduling for video mode panel.

	 *

techpack/display/msm/dsi/dsi_ctrl_hw.h

+10 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DSI_CTRL_HW_H_
@@ -866,6 +867,15 @@ struct dsi_ctrl_hw_ops { 
	void (*reset_trig_ctrl)(struct dsi_ctrl_hw *ctrl,

			struct dsi_host_common_cfg *cfg);



	/**

	 * hw.ops.init_cmddma_trig_ctrl() - Initialize the default trigger used

	 *                             for command mode DMA path.

	 * @ctrl:	Pointer to the controller host hardware.

	 * @cfg:	Common configuration parameters.

	 */

	void (*init_cmddma_trig_ctrl)(struct dsi_ctrl_hw *ctrl,

			struct dsi_host_common_cfg *cfg);



	/**

	 * hw.ops.log_line_count() - reads the MDP interface line count

	 *			     registers.

techpack/display/msm/dsi/dsi_ctrl_hw_2_2.c

+7 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 */

#include <linux/iopoll.h>

#include "dsi_ctrl_hw.h"
@@ -243,14 +244,16 @@ void dsi_ctrl_hw_22_configure_cmddma_window(struct dsi_ctrl_hw *ctrl, 
void dsi_ctrl_hw_22_reset_trigger_controls(struct dsi_ctrl_hw *ctrl,

				       struct dsi_host_common_cfg *cfg)

{

	u32 reg = 0;

	u32 reg;

	const u8 trigger_map[DSI_TRIGGER_MAX] = {

		0x0, 0x2, 0x1, 0x4, 0x5, 0x6 };



	reg |= (cfg->te_mode == DSI_TE_ON_EXT_PIN) ? BIT(31) : 0;

	reg |= (trigger_map[cfg->dma_cmd_trigger] & 0x7);

	reg |= (trigger_map[cfg->mdp_cmd_trigger] & 0x7) << 4;

	reg = DSI_R32(ctrl, DSI_TRIG_CTRL);

	reg &= ~BIT(16); /* Reset DMA_TRG_MUX */

	reg &= ~(0xF); /* Reset DMA_TRIGGER_SEL */

	reg |= (trigger_map[cfg->dma_cmd_trigger] & 0xF);

	DSI_W32(ctrl, DSI_TRIG_CTRL, reg);



	DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL2, 0x0);

	DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, 0x0);

	ctrl->reset_trig_ctrl = false;