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Commit ded220e2 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
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drm/i915: Simplify ironlake_crtc_compute_clock() CPU eDP case 



None of the code in ironlake_crtc_compute_clock() is relevant for CPU
eDP. The CPU eDP PLL is turned on and off in ironlake_edp_pll_{on,off}
from the DP code and that doesn't depend on the crtc_state->dpll values,
so just return early in that case.

v2: Rebase without patch that drops lvds downclock code. (Ville)
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458576016-30348-9-git-send-email-ander.conselvan.de.oliveira@intel.com
parent fade85ae

drivers/gpu/drm/i915/intel_display.c

+23 −24
Original line number Diff line number Diff line
@@ -8800,13 +8800,16 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 
	intel_clock_t clock, reduced_clock;

	u32 dpll = 0, fp = 0, fp2 = 0;

	bool has_reduced_clock = false;

	bool is_lvds = false;

	struct intel_shared_dpll *pll;



	memset(&crtc_state->dpll_hw_state, 0,

	       sizeof(crtc_state->dpll_hw_state));



	is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);

	crtc->lowfreq_avail = false;



	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */

	if (!crtc_state->has_pch_encoder)

		return 0;



	if (!crtc_state->clock_set) {

		if (!ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
@@ -8824,8 +8827,6 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 
		crtc_state->dpll.p2 = clock.p2;

	}



	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */

	if (crtc_state->has_pch_encoder) {

	fp = i9xx_dpll_compute_fp(&crtc_state->dpll);

	if (has_reduced_clock)

		fp2 = i9xx_dpll_compute_fp(&reduced_clock);
@@ -8846,12 +8847,10 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, 
				 pipe_name(crtc->pipe));

		return -EINVAL;

	}

	}



	if (is_lvds && has_reduced_clock)

	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&

	    has_reduced_clock)

		crtc->lowfreq_avail = true;

	else

		crtc->lowfreq_avail = false;



	return 0;

}