Merge with /home/shaggy/git/linus-clean/ (de8fd087) · Commits · e / devices / android_kernel_fairphone_FP5

arch/arm/boot/compressed/head-shark.S

+33 −9

Original line number	Diff line number	Diff line
		@@ -63,8 +63,8 @@ __beginning: mov r4, r0 @ save the entry to the firmware

		mov pc, r2

		__copy_target: .long 0x08508000
		__copy_end: .long 0x08608000
		__copy_target: .long 0x08507FFC
		__copy_end: .long 0x08607FFC

		.word _start
		.word __bss_start
		@@ -73,9 +73,10 @@ __copy_end: .long 0x08608000
		__temp_stack: .space 128

		__mmu_off:
		adr r0, __ofw_data
		adr r0, __ofw_data @ read the 1. entry of the memory map
		ldr r0, [r0, #4]
		orr r0, r0, #0x00600000
		sub r0, r0, #4

		ldr r1, __copy_end
		ldr r3, __copy_target
		@@ -89,20 +90,43 @@ __mmu_off:
		* from 0x08500000 to 0x08508000 if we have only 8MB
		*/

		/* As we get more 2.6-kernels it gets more and more
		* uncomfortable to be bound to kernel images of 1MB only.
		* So we add a loop here, to be able to copy some more.
		* Alexander Schulz 2005-07-17
		*/

		mov r4, #3 @ How many megabytes to copy


		__MoveCode: sub r4, r4, #1

		__Copy: ldr r2, [r0], #-4
		str r2, [r1], #-4
		teq r1, r3
		bne __Copy

		/* The firmware maps us in blocks of 1 MB, the next block is
		_below_ the last one. So our decrementing source pointer
		ist right here, but the destination pointer must be increased
		by 2 MB */
		add r1, r1, #0x00200000
		add r3, r3, #0x00100000

		teq r4, #0
		bne __MoveCode


		/* and jump to it */
		adr r2, __go_on
		adr r0, __ofw_data
		adr r2, __go_on @ where we want to jump
		adr r0, __ofw_data @ read the 1. entry of the memory map
		ldr r0, [r0, #4]
		sub r2, r2, r0
		sub r2, r2, #0x00500000
		ldr r0, __copy_target
		sub r2, r2, r0 @ we are mapped add 0e50 now, sub that (-0e00)
		sub r2, r2, #0x00500000 @ -0050
		ldr r0, __copy_target @ and add 0850 8000 instead
		add r0, r0, #4
		add r2, r2, r0
		mov pc, r2
		mov pc, r2 @ and jump there

		__go_on:
		adr sp, __temp_stack

arch/arm/configs/bast_defconfig

+0 −1

Original line number	Diff line number	Diff line
		@@ -561,7 +561,6 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
		#
		CONFIG_SERIAL_S3C2410=y
		CONFIG_SERIAL_S3C2410_CONSOLE=y
		CONFIG_SERIAL_BAST_SIO=y
		CONFIG_SERIAL_CORE=y
		CONFIG_SERIAL_CORE_CONSOLE=y
		CONFIG_UNIX98_PTYS=y

arch/arm/configs/s3c2410_defconfig

+0 −1

Original line number	Diff line number	Diff line
		@@ -570,7 +570,6 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
		#
		CONFIG_SERIAL_S3C2410=y
		CONFIG_SERIAL_S3C2410_CONSOLE=y
		CONFIG_SERIAL_BAST_SIO=y
		CONFIG_SERIAL_CORE=y
		CONFIG_SERIAL_CORE_CONSOLE=y
		CONFIG_UNIX98_PTYS=y

arch/arm/kernel/smp.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -78,7 +78,7 @@ struct smp_call_struct {
		static struct smp_call_struct * volatile smp_call_function_data;
		static DEFINE_SPINLOCK(smp_call_function_lock);

		int __init __cpu_up(unsigned int cpu)
		int __cpuinit __cpu_up(unsigned int cpu)
		{
		struct task_struct *idle;
		pgd_t *pgd;
		@@ -159,7 +159,7 @@ int __init __cpu_up(unsigned int cpu)
		* This is the secondary CPU boot entry. We're using this CPUs
		* idle thread stack, but a set of temporary page tables.
		*/
		asmlinkage void __init secondary_start_kernel(void)
		asmlinkage void __cpuinit secondary_start_kernel(void)
		{
		struct mm_struct *mm = &init_mm;
		unsigned int cpu = smp_processor_id();
		@@ -209,7 +209,7 @@ asmlinkage void __init secondary_start_kernel(void)
		* Called by both boot and secondaries to move global data into
		* per-processor storage.
		*/
		void __init smp_store_cpu_info(unsigned int cpuid)
		void __cpuinit smp_store_cpu_info(unsigned int cpuid)
		{
		struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);

arch/arm/mach-integrator/platsmp.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -27,12 +27,12 @@ extern void integrator_secondary_startup(void);
		* control for which core is the next to come out of the secondary
		* boot "holding pen"
		*/
		volatile int __initdata pen_release = -1;
		unsigned long __initdata phys_pen_release = 0;
		volatile int __cpuinitdata pen_release = -1;
		unsigned long __cpuinitdata phys_pen_release = 0;

		static DEFINE_SPINLOCK(boot_lock);

		void __init platform_secondary_init(unsigned int cpu)
		void __cpuinit platform_secondary_init(unsigned int cpu)
		{
		/*
		* the primary core may have used a "cross call" soft interrupt
		@@ -61,7 +61,7 @@ void __init platform_secondary_init(unsigned int cpu)
		spin_unlock(&boot_lock);
		}

		int __init boot_secondary(unsigned int cpu, struct task_struct *idle)
		int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
		{
		unsigned long timeout;