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Commit de862b48 authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
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[MIPS] TX49XX has prefetch. 


    
The TX49XX has the prefetch instruction.  It supports only Pref_Load
(hint 0).  Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
    
Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c6281edb

arch/mips/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -1160,6 +1160,7 @@ config CPU_R4X00 
config CPU_TX49XX

config CPU_TX49XX

	bool "R49XX"

	bool "R49XX"

	depends on SYS_HAS_CPU_TX49XX

	depends on SYS_HAS_CPU_TX49XX

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_64BIT_KERNEL

arch/mips/mm/c-r4k.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -786,6 +786,7 @@ static void __init probe_pcache(void) 
		c->dcache.waybit = 0;

		c->dcache.waybit = 0;





		c->options |= MIPS_CPU_CACHE_CDEX_P;

		c->options |= MIPS_CPU_CACHE_CDEX_P;

		c->options |= MIPS_CPU_PREFETCH;

		break;

		break;





	case CPU_R4000PC:

	case CPU_R4000PC:

arch/mips/mm/pg-r4k.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -124,7 +124,7 @@ static inline void build_nop(void) 




static inline void build_src_pref(int advance)

static inline void build_src_pref(int advance)

{

{

	if (!(load_offset & (cpu_dcache_line_size() - 1))) {

	if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {

		union mips_instruction mi;

		union mips_instruction mi;





		mi.i_format.opcode     = pref_op;

		mi.i_format.opcode     = pref_op;
@@ -166,7 +166,7 @@ static inline void build_load_reg(int reg) 




static inline void build_dst_pref(int advance)

static inline void build_dst_pref(int advance)

{

{

	if (!(store_offset & (cpu_dcache_line_size() - 1))) {

	if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {

		union mips_instruction mi;

		union mips_instruction mi;





		mi.i_format.opcode     = pref_op;

		mi.i_format.opcode     = pref_op;
@@ -340,6 +340,12 @@ void __init build_clear_page(void) 




	if (cpu_has_prefetch) {

	if (cpu_has_prefetch) {

		switch (current_cpu_data.cputype) {

		switch (current_cpu_data.cputype) {

		case CPU_TX49XX:

			/* TX49 supports only Pref_Load */

			pref_offset_clear = 0;

			pref_offset_copy = 0;

			break;



		case CPU_RM9000:

		case CPU_RM9000:

			/*

			/*

			 * As a workaround for erratum G105 which make the

			 * As a workaround for erratum G105 which make the