Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit de4a2967 authored by SivapiriyanKumarasamy's avatar SivapiriyanKumarasamy Committed by Alex Deucher
Browse files

drm/amd/display: Apply VQ adjustments in MPO case 



Signed-off-by: default avatarSivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c9ef081d

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −1
Original line number Diff line number Diff line
@@ -1137,6 +1137,7 @@ static enum surface_update_type get_plane_info_update_type( 
	temp_plane_info.plane_size = u->surface->plane_size;

	temp_plane_info.rotation = u->surface->rotation;

	temp_plane_info.stereo_format = u->surface->stereo_format;

	temp_plane_info.input_csc_enabled = u->surface->input_csc_color_matrix.enable_adjustment;



	if (surface_index == 0)

		temp_plane_info.visible = u->plane_info->visible;
@@ -1217,7 +1218,8 @@ static enum surface_update_type det_surface_update( 
		overall_type = type;



	if (u->in_transfer_func ||

		u->hdr_static_metadata) {

		u->hdr_static_metadata ||

		u->input_csc_color_matrix) {

		if (overall_type < UPDATE_TYPE_MED)

			overall_type = UPDATE_TYPE_MED;

	}

drivers/gpu/drm/amd/display/dc/dc.h

+7 −0
Original line number Diff line number Diff line
@@ -431,6 +431,9 @@ struct dc_plane_state { 


	struct dc_gamma *gamma_correction;

	struct dc_transfer_func *in_transfer_func;

	struct dc_bias_and_scale *bias_and_scale;

	struct csc_transform input_csc_color_matrix;

	struct fixed31_32 coeff_reduction_factor;



	// sourceContentAttribute cache

	bool is_source_input_valid;
@@ -468,6 +471,7 @@ struct dc_plane_info { 
	bool horizontal_mirror;

	bool visible;

	bool per_pixel_alpha;

	bool input_csc_enabled;

};



struct dc_scaling_info {
@@ -491,6 +495,9 @@ struct dc_surface_update { 
	struct dc_gamma *gamma;

	struct dc_transfer_func *in_transfer_func;

	struct dc_hdr_static_metadata *hdr_static_metadata;



	struct csc_transform *input_csc_color_matrix;

	struct fixed31_32 *coeff_reduction_factor;

};



/*

drivers/gpu/drm/amd/display/dc/dc_types.h

+0 −5
Original line number Diff line number Diff line
@@ -638,11 +638,6 @@ struct colorspace_transform { 
	bool enable_remap;

};



struct csc_transform {

	uint16_t matrix[12];

	bool enable_adjustment;

};



enum i2c_mot_mode {

	I2C_MOT_UNDEF,

	I2C_MOT_TRUE,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c

+26 −5
Original line number Diff line number Diff line
@@ -264,8 +264,10 @@ static void dpp1_set_degamma_format_float( 


void dpp1_cnv_setup (

		struct dpp *dpp_base,

		enum surface_pixel_format input_format,

		enum expansion_mode mode)

		enum surface_pixel_format format,

		enum expansion_mode mode,

		struct csc_transform input_csc_color_matrix,

		enum dc_color_space input_color_space)

{

	uint32_t pixel_format;

	uint32_t alpha_en;
@@ -275,8 +277,10 @@ void dpp1_cnv_setup ( 
	bool is_float;

	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

	bool force_disable_cursor = false;

	struct out_csc_color_matrix tbl_entry;

	int i = 0;



	dpp1_setup_format_flags(input_format, &fmt);

	dpp1_setup_format_flags(format, &fmt);

	alpha_en = 1;

	pixel_format = 0;

	color_space = COLOR_SPACE_SRGB;
@@ -306,7 +310,7 @@ void dpp1_cnv_setup ( 


	dpp1_set_degamma_format_float(dpp_base, is_float);



	switch (input_format) {

	switch (format) {

	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:

		pixel_format = 1;

		break;
@@ -362,7 +366,23 @@ void dpp1_cnv_setup ( 
			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);

	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);



	dpp1_program_input_csc(dpp_base, color_space, select);

	// if input adjustments exist, program icsc with those values



	if (input_csc_color_matrix.enable_adjustment

				== true) {

		for (i = 0; i < 12; i++)

			tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];



		tbl_entry.color_space = input_color_space;



		if (color_space >= COLOR_SPACE_YCBCR601)

			select = INPUT_CSC_SELECT_ICSC;

		else

			select = INPUT_CSC_SELECT_BYPASS;



		dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);

	} else

		dpp1_program_input_csc(dpp_base, color_space, select, NULL);



	if (force_disable_cursor) {

		REG_UPDATE(CURSOR_CONTROL,
@@ -435,6 +455,7 @@ static const struct dpp_funcs dcn10_dpp_funcs = { 
		.opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,

		.opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,

		.opp_set_regamma_mode = dpp1_cm_set_regamma_mode,

		.ipp_program_bias_and_scale = dpp1_program_bias_and_scale,

		.ipp_set_degamma = dpp1_set_degamma,

		.ipp_program_input_lut		= dpp1_program_input_lut,

		.ipp_program_degamma_pwl	= dpp1_set_degamma_pwl,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+36 −11
Original line number Diff line number Diff line
@@ -73,9 +73,6 @@ 
	SRI(RECOUT_START, DSCL, id), \

	SRI(RECOUT_SIZE, DSCL, id), \

	SRI(OBUF_CONTROL, DSCL, id), \

	SRI(CM_ICSC_CONTROL, CM, id), \

	SRI(CM_ICSC_C11_C12, CM, id), \

	SRI(CM_ICSC_C33_C34, CM, id), \

	SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \

	SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \

	SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
@@ -127,6 +124,12 @@ 
	SRI(CM_OCSC_CONTROL, CM, id), \

	SRI(CM_OCSC_C11_C12, CM, id), \

	SRI(CM_OCSC_C33_C34, CM, id), \

	SRI(CM_ICSC_CONTROL, CM, id), \

	SRI(CM_ICSC_C11_C12, CM, id), \

	SRI(CM_ICSC_C33_C34, CM, id), \

	SRI(CM_BNS_VALUES_R, CM, id), \

	SRI(CM_BNS_VALUES_G, CM, id), \

	SRI(CM_BNS_VALUES_B, CM, id), \

	SRI(CM_MEM_PWR_CTRL, CM, id), \

	SRI(CM_RGAM_LUT_DATA, CM, id), \

	SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
@@ -236,11 +239,6 @@ 
	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\

	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \

	TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \

	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \

	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \

	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \

	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
@@ -329,6 +327,17 @@ 
	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \

	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \

	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \

	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \

	TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \

	TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \

	TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
@@ -913,6 +922,12 @@ 
	type CM_ICSC_C12; \

	type CM_ICSC_C33; \

	type CM_ICSC_C34; \

	type CM_BNS_BIAS_R; \

	type CM_BNS_BIAS_G; \

	type CM_BNS_BIAS_B; \

	type CM_BNS_SCALE_R; \

	type CM_BNS_SCALE_G; \

	type CM_BNS_SCALE_B; \

	type CM_DGAM_RAMB_EXP_REGION_START_B; \

	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \

	type CM_DGAM_RAMB_EXP_REGION_START_G; \
@@ -1206,6 +1221,9 @@ struct dcn_dpp_registers { 
	uint32_t CM_ICSC_CONTROL;

	uint32_t CM_ICSC_C11_C12;

	uint32_t CM_ICSC_C33_C34;

	uint32_t CM_BNS_VALUES_R;

	uint32_t CM_BNS_VALUES_G;

	uint32_t CM_BNS_VALUES_B;

	uint32_t CM_DGAM_RAMB_START_CNTL_B;

	uint32_t CM_DGAM_RAMB_START_CNTL_G;

	uint32_t CM_DGAM_RAMB_START_CNTL_R;
@@ -1310,7 +1328,12 @@ void dpp1_power_on_degamma_lut( 
void dpp1_program_input_csc(

		struct dpp *dpp_base,

		enum dc_color_space color_space,

		enum dcn10_input_csc_select select);

		enum dcn10_input_csc_select select,

		const struct out_csc_color_matrix *tbl_entry);



void dpp1_program_bias_and_scale(

		struct dpp *dpp_base,

		struct dc_bias_and_scale *params);



void dpp1_program_input_lut(

		struct dpp *dpp_base,
@@ -1372,8 +1395,10 @@ void dpp1_dscl_set_scaler_manual_scale( 


void dpp1_cnv_setup (

		struct dpp *dpp_base,

		enum surface_pixel_format input_format,

		enum expansion_mode mode);

		enum surface_pixel_format format,

		enum expansion_mode mode,

		struct csc_transform input_csc_color_matrix,

		enum dc_color_space input_color_space);



void dpp1_full_bypass(struct dpp *dpp_base);