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Commit de0f51e4 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Jonathan Corbet
Browse files

docs: core-api: add cachetlb documentation 



The cachetlb.txt is already in ReST format. So, move it to the
core-api guide, where it belongs.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: default avatarJonathan Corbet <corbet@lwn.net>
parent fe8703cc

Documentation/00-INDEX

+0 −2
Original line number Diff line number Diff line
@@ -76,8 +76,6 @@ bus-devices/ 
	- directory with info on TI GPMC (General Purpose Memory Controller)

bus-virt-phys-mapping.txt

	- how to access I/O mapped memory from within device drivers.

cachetlb.txt

	- describes the cache/TLB flushing interfaces Linux uses.

cdrom/

	- directory with information on the CD-ROM drivers that Linux has.

cgroup-v1/

Documentation/core-api/index.rst

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@@ -14,6 +14,7 @@ Core utilities 
   kernel-api

   assoc_array

   atomic_ops

   cachetlb

   refcount-vs-atomic

   cpu_hotplug

   idr

Documentation/memory-barriers.txt

+1 −1
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@@ -2903,7 +2903,7 @@ is discarded from the CPU's cache and reloaded. To deal with this, the 
appropriate part of the kernel must invalidate the overlapping bits of the

cache on each CPU.



See Documentation/cachetlb.txt for more information on cache management.

See Documentation/core-api/cachetlb.rst for more information on cache management.





CACHE COHERENCY VS MMIO

Documentation/translations/ko_KR/memory-barriers.txt

+1 −1
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@@ -2846,7 +2846,7 @@ CPU 의 캐시에서 RAM 으로 쓰여지는 더티 캐시 라인에 의해 덮 
문제를 해결하기 위해선, 커널의 적절한 부분에서 각 CPU 의 캐시 안의 문제가 되는

비트들을 무효화 시켜야 합니다.



캐시 관리에 대한 더 많은 정보를 위해선 Documentation/cachetlb.txt 를

캐시 관리에 대한 더 많은 정보를 위해선 Documentation/core-api/cachetlb.rst 를

참고하세요.