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Commit dde87f7f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "interconnect: qcom: Add SDC1 master for Shima"

parents 85f242f7 649dce90

drivers/interconnect/qcom/shima.c

+10 −0
Original line number Diff line number Diff line
@@ -47,6 +47,15 @@ static struct qcom_icc_node qnm_a1noc_cfg = { 
	.links = { SLAVE_SERVICE_A1NOC },

};



static struct qcom_icc_node xm_sdc1 = {

	.name = "xm_sdc1",

	.id = MASTER_SDCC_1,

	.channels = 1,

	.buswidth = 8,

	.num_links = 1,

	.links = { SLAVE_A1NOC_SNOC },

};



static struct qcom_icc_node xm_sdc4 = {

	.name = "xm_sdc4",

	.id = MASTER_SDCC_4,
@@ -1558,6 +1567,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { 
	[MASTER_QSPI_0] = &qhm_qspi,

	[MASTER_QUP_1] = &qhm_qup1,

	[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,

	[MASTER_SDCC_1] = &xm_sdc1,

	[MASTER_SDCC_4] = &xm_sdc4,

	[MASTER_UFS_MEM] = &xm_ufs_mem,

	[MASTER_USB3_0] = &xm_usb3_0,

include/dt-bindings/interconnect/qcom,shima.h

+5 −4
Original line number Diff line number Diff line
@@ -52,10 +52,11 @@ 
#define MASTER_PCIE_1				43

#define MASTER_QDSS_DAP				44

#define MASTER_QDSS_ETR				45

#define MASTER_SDCC_2				46

#define MASTER_SDCC_4				47

#define MASTER_UFS_MEM				48

#define MASTER_USB3_0				49

#define MASTER_SDCC_1				46

#define MASTER_SDCC_2				47

#define MASTER_SDCC_4				48

#define MASTER_UFS_MEM				49

#define MASTER_USB3_0				50

#define SLAVE_EBI1				512

#define SLAVE_AHB2PHY_SOUTH				513

#define SLAVE_AHB2PHY_NORTH				514