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Commit ddc07a38 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: remove interlace scaling adjustment 



We do not need to adjust surface scaling when p2i is enabled
and we do not support interlaced timing otherwise

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c9915523

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+0 −9
Original line number Diff line number Diff line
@@ -1115,9 +1115,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 
	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(

			pipe_ctx->plane_state->format);



	if (pipe_ctx->stream->timing.flags.INTERLACE)

		pipe_ctx->stream->dst.height *= 2;



	calculate_scaling_ratios(pipe_ctx);



	calculate_viewport(pipe_ctx);
@@ -1138,9 +1135,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 


	pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;

	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;

	if (pipe_ctx->stream->timing.flags.INTERLACE)

		pipe_ctx->plane_res.scl_data.v_active *= 2;





	/* Taps calculations */

	if (pipe_ctx->plane_res.xfm != NULL)
@@ -1185,9 +1179,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) 
				plane_state->dst_rect.x,

				plane_state->dst_rect.y);



	if (pipe_ctx->stream->timing.flags.INTERLACE)

		pipe_ctx->stream->dst.height /= 2;



	return res;

}