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Commit ddb49277 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: constify structs with function pointers 



Now that the last of the runtime modifications to adreno_gpudev are gone
finally mark it and the other structs as const to protect the function
pointers within.

Change-Id: Ic0dedbad25b39b5df0fdd565a494164e1588c9a1
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent d1dfa3f1

drivers/gpu/msm/adreno.c

+21 −21
Original line number Original line Diff line number Diff line
@@ -145,7 +145,7 @@ void adreno_reglist_write(struct adreno_device *adreno_dev, 
void adreno_readreg64(struct adreno_device *adreno_dev,

void adreno_readreg64(struct adreno_device *adreno_dev,

		enum adreno_regs lo, enum adreno_regs hi, uint64_t *val)

		enum adreno_regs lo, enum adreno_regs hi, uint64_t *val)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int val_lo = 0, val_hi = 0;

	unsigned int val_lo = 0, val_hi = 0;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -168,7 +168,7 @@ void adreno_readreg64(struct adreno_device *adreno_dev, 
void adreno_writereg64(struct adreno_device *adreno_dev,

void adreno_writereg64(struct adreno_device *adreno_dev,

		enum adreno_regs lo, enum adreno_regs hi, uint64_t val)

		enum adreno_regs lo, enum adreno_regs hi, uint64_t val)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (adreno_checkreg_off(adreno_dev, lo))

	if (adreno_checkreg_off(adreno_dev, lo))

		kgsl_regwrite(KGSL_DEVICE(adreno_dev),

		kgsl_regwrite(KGSL_DEVICE(adreno_dev),
@@ -283,7 +283,7 @@ static int _get_counter(struct adreno_device *adreno_dev, 
 */

 */

void adreno_fault_detect_start(struct adreno_device *adreno_dev)

void adreno_fault_detect_start(struct adreno_device *adreno_dev)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);

	unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);





	if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))

	if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))
@@ -311,7 +311,7 @@ void adreno_fault_detect_start(struct adreno_device *adreno_dev) 
 */

 */

void adreno_fault_detect_stop(struct adreno_device *adreno_dev)

void adreno_fault_detect_stop(struct adreno_device *adreno_dev)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);

	unsigned int i, j = ARRAY_SIZE(adreno_ft_regs_default);





	if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))

	if (!test_bit(ADRENO_DEVICE_SOFT_FAULT_DETECT, &adreno_dev->priv))
@@ -508,7 +508,7 @@ static struct input_handler adreno_input_handler = { 
 */

 */

static void _soft_reset(struct adreno_device *adreno_dev)

static void _soft_reset(struct adreno_device *adreno_dev)

{

{

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int reg;

	unsigned int reg;





	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);
@@ -571,7 +571,7 @@ void adreno_cp_callback(struct adreno_device *adreno_dev, int bit) 
static irqreturn_t adreno_irq_handler(struct kgsl_device *device)

static irqreturn_t adreno_irq_handler(struct kgsl_device *device)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	irqreturn_t ret;

	irqreturn_t ret;





	atomic_inc(&adreno_dev->pending_irq_refcnt);

	atomic_inc(&adreno_dev->pending_irq_refcnt);
@@ -590,7 +590,7 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device) 
}

}





irqreturn_t adreno_irq_callbacks(struct adreno_device *adreno_dev,

irqreturn_t adreno_irq_callbacks(struct adreno_device *adreno_dev,

		struct adreno_irq_funcs *funcs, u32 status)

		const struct adreno_irq_funcs *funcs, u32 status)

{

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	irqreturn_t ret = IRQ_NONE;

	irqreturn_t ret = IRQ_NONE;
@@ -1493,7 +1493,7 @@ static void adreno_unbind(struct device *dev) 
{

{

	struct adreno_device *adreno_dev;

	struct adreno_device *adreno_dev;

	struct kgsl_device *device;

	struct kgsl_device *device;

	struct adreno_gpudev *gpudev;

	const struct adreno_gpudev *gpudev;





	device = dev_get_drvdata(dev);

	device = dev_get_drvdata(dev);

	if (!device)

	if (!device)
@@ -1612,7 +1612,7 @@ static int adreno_pm_suspend(struct device *dev) 




static void adreno_fault_detect_init(struct adreno_device *adreno_dev)

static void adreno_fault_detect_init(struct adreno_device *adreno_dev)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int i;

	int i;





	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SOFT_FAULT_DETECT))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SOFT_FAULT_DETECT))
@@ -1651,7 +1651,7 @@ static void adreno_fault_detect_init(struct adreno_device *adreno_dev) 
static int adreno_init(struct kgsl_device *device)

static int adreno_init(struct kgsl_device *device)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int ret;

	int ret;





	ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);

	ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);
@@ -2003,7 +2003,7 @@ void adreno_clear_dcvs_counters(struct adreno_device *adreno_dev) 
static int _adreno_start(struct adreno_device *adreno_dev)

static int _adreno_start(struct adreno_device *adreno_dev)

{

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int status;

	int status;

	unsigned int state = device->state;

	unsigned int state = device->state;

	bool regulator_left_on;

	bool regulator_left_on;
@@ -2126,7 +2126,7 @@ int adreno_start(struct kgsl_device *device, int priority) 
static int adreno_stop(struct kgsl_device *device)

static int adreno_stop(struct kgsl_device *device)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int error = 0;

	int error = 0;





	if (!test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv))

	if (!test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv))
@@ -2174,7 +2174,7 @@ static int adreno_stop(struct kgsl_device *device) 
int adreno_reset(struct kgsl_device *device, int fault)

int adreno_reset(struct kgsl_device *device, int fault)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int ret = -EINVAL;

	int ret = -EINVAL;

	int i;

	int i;
@@ -2649,7 +2649,7 @@ bool adreno_irq_pending(struct adreno_device *adreno_dev) 
static int adreno_soft_reset(struct kgsl_device *device)

static int adreno_soft_reset(struct kgsl_device *device)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	int ret;

	int ret;





	/*

	/*
@@ -2722,7 +2722,7 @@ static int adreno_soft_reset(struct kgsl_device *device) 




static bool adreno_isidle(struct adreno_device *adreno_dev)

static bool adreno_isidle(struct adreno_device *adreno_dev)

{

{

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_ringbuffer *rb;

	struct adreno_ringbuffer *rb;

	int i;

	int i;
@@ -2983,7 +2983,7 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, 
		unsigned int fence_mask)

		unsigned int fence_mask)

{

{

	unsigned int status, i;

	unsigned int status, i;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int reg_offset = gpudev->reg_offsets[offset];

	unsigned int reg_offset = gpudev->reg_offsets[offset];





	adreno_writereg(adreno_dev, offset, val);

	adreno_writereg(adreno_dev, offset, val);
@@ -3382,7 +3382,7 @@ static void adreno_power_stats(struct kgsl_device *device, 
				struct kgsl_power_stats *stats)

				struct kgsl_power_stats *stats)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;

	struct adreno_busy_data *busy = &adreno_dev->busy_data;

	struct adreno_busy_data *busy = &adreno_dev->busy_data;

	int64_t adj = 0;

	int64_t adj = 0;
@@ -3504,7 +3504,7 @@ static int adreno_regulator_enable(struct kgsl_device *device) 
{

{

	int ret = 0;

	int ret = 0;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);





	if (gpudev->regulator_enable &&

	if (gpudev->regulator_enable &&

		!test_bit(ADRENO_DEVICE_GPU_REGULATOR_ENABLED,

		!test_bit(ADRENO_DEVICE_GPU_REGULATOR_ENABLED,
@@ -3520,7 +3520,7 @@ static int adreno_regulator_enable(struct kgsl_device *device) 
static bool adreno_is_hw_collapsible(struct kgsl_device *device)

static bool adreno_is_hw_collapsible(struct kgsl_device *device)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);





	/*

	/*

	 * Skip power collapse for A304, if power ctrl flag is set to

	 * Skip power collapse for A304, if power ctrl flag is set to
@@ -3538,7 +3538,7 @@ static bool adreno_is_hw_collapsible(struct kgsl_device *device) 
static void adreno_regulator_disable(struct kgsl_device *device)

static void adreno_regulator_disable(struct kgsl_device *device)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);





	if (gpudev->regulator_disable &&

	if (gpudev->regulator_disable &&

		test_bit(ADRENO_DEVICE_GPU_REGULATOR_ENABLED,

		test_bit(ADRENO_DEVICE_GPU_REGULATOR_ENABLED,
@@ -3553,7 +3553,7 @@ static void adreno_pwrlevel_change_settings(struct kgsl_device *device, 
		unsigned int prelevel, unsigned int postlevel, bool post)

		unsigned int prelevel, unsigned int postlevel, bool post)

{

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);





	if (gpudev->pwrlevel_change_settings)

	if (gpudev->pwrlevel_change_settings)

		gpudev->pwrlevel_change_settings(adreno_dev, prelevel,

		gpudev->pwrlevel_change_settings(adreno_dev, prelevel,

drivers/gpu/msm/adreno.h

+16 −16
Original line number Original line Diff line number Diff line
@@ -390,7 +390,7 @@ struct adreno_gpu_core { 
	 */

	 */

	const char *compatible;

	const char *compatible;

	unsigned long features;

	unsigned long features;

	struct adreno_gpudev *gpudev;

	const struct adreno_gpudev *gpudev;

	const struct adreno_perfcounters *perfcounters;

	const struct adreno_perfcounters *perfcounters;

	unsigned long gmem_base;

	unsigned long gmem_base;

	size_t gmem_size;

	size_t gmem_size;
@@ -879,14 +879,14 @@ extern unsigned int *adreno_ft_regs; 
extern unsigned int adreno_ft_regs_num;

extern unsigned int adreno_ft_regs_num;

extern unsigned int *adreno_ft_regs_val;

extern unsigned int *adreno_ft_regs_val;





extern struct adreno_gpudev adreno_a3xx_gpudev;

extern const struct adreno_gpudev adreno_a3xx_gpudev;

extern struct adreno_gpudev adreno_a5xx_gpudev;

extern const struct adreno_gpudev adreno_a5xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gpudev;

extern const struct adreno_gpudev adreno_a6xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gmu_gpudev;

extern const struct adreno_gpudev adreno_a6xx_gmu_gpudev;

extern struct adreno_gpudev adreno_a6xx_rgmu_gpudev;

extern const struct adreno_gpudev adreno_a6xx_rgmu_gpudev;

extern struct adreno_gpudev adreno_a619_holi_gpudev;

extern const struct adreno_gpudev adreno_a619_holi_gpudev;

extern struct adreno_gpudev adreno_a630_gpudev;

extern const struct adreno_gpudev adreno_a630_gpudev;

extern struct adreno_gpudev adreno_a6xx_hwsched_gpudev;

extern const struct adreno_gpudev adreno_a6xx_hwsched_gpudev;





extern int adreno_wake_nice;

extern int adreno_wake_nice;

extern unsigned int adreno_wake_timeout;

extern unsigned int adreno_wake_timeout;
@@ -1133,7 +1133,7 @@ static inline int adreno_is_a640v2(struct adreno_device *adreno_dev) 
static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev,

static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev,

					enum adreno_regs offset_name)

					enum adreno_regs offset_name)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (offset_name >= ADRENO_REG_REGISTER_MAX ||

	if (offset_name >= ADRENO_REG_REGISTER_MAX ||

		gpudev->reg_offsets[offset_name] == ADRENO_REG_UNUSED)

		gpudev->reg_offsets[offset_name] == ADRENO_REG_UNUSED)
@@ -1163,7 +1163,7 @@ static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev, 
static inline void adreno_readreg(struct adreno_device *adreno_dev,

static inline void adreno_readreg(struct adreno_device *adreno_dev,

				enum adreno_regs offset_name, unsigned int *val)

				enum adreno_regs offset_name, unsigned int *val)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (adreno_checkreg_off(adreno_dev, offset_name))

	if (adreno_checkreg_off(adreno_dev, offset_name))

		kgsl_regread(KGSL_DEVICE(adreno_dev),

		kgsl_regread(KGSL_DEVICE(adreno_dev),
@@ -1182,7 +1182,7 @@ static inline void adreno_readreg(struct adreno_device *adreno_dev, 
static inline void adreno_writereg(struct adreno_device *adreno_dev,

static inline void adreno_writereg(struct adreno_device *adreno_dev,

				enum adreno_regs offset_name, unsigned int val)

				enum adreno_regs offset_name, unsigned int val)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (adreno_checkreg_off(adreno_dev, offset_name))

	if (adreno_checkreg_off(adreno_dev, offset_name))

		kgsl_regwrite(KGSL_DEVICE(adreno_dev),

		kgsl_regwrite(KGSL_DEVICE(adreno_dev),
@@ -1198,7 +1198,7 @@ static inline void adreno_writereg(struct adreno_device *adreno_dev, 
static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev,

static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev,

				enum adreno_regs offset_name)

				enum adreno_regs offset_name)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (!adreno_checkreg_off(adreno_dev, offset_name))

	if (!adreno_checkreg_off(adreno_dev, offset_name))

		return ADRENO_REG_REGISTER_MAX;

		return ADRENO_REG_REGISTER_MAX;
@@ -1215,7 +1215,7 @@ static inline unsigned int adreno_getreg(struct adreno_device *adreno_dev, 
static inline void adreno_read_gmureg(struct adreno_device *adreno_dev,

static inline void adreno_read_gmureg(struct adreno_device *adreno_dev,

				enum adreno_regs offset_name, unsigned int *val)

				enum adreno_regs offset_name, unsigned int *val)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (adreno_checkreg_off(adreno_dev, offset_name))

	if (adreno_checkreg_off(adreno_dev, offset_name))

		gmu_core_regread(KGSL_DEVICE(adreno_dev),

		gmu_core_regread(KGSL_DEVICE(adreno_dev),
@@ -1234,7 +1234,7 @@ static inline void adreno_read_gmureg(struct adreno_device *adreno_dev, 
static inline void adreno_write_gmureg(struct adreno_device *adreno_dev,

static inline void adreno_write_gmureg(struct adreno_device *adreno_dev,

				enum adreno_regs offset_name, unsigned int val)

				enum adreno_regs offset_name, unsigned int val)

{

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	const struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);





	if (adreno_checkreg_off(adreno_dev, offset_name))

	if (adreno_checkreg_off(adreno_dev, offset_name))

		gmu_core_regwrite(KGSL_DEVICE(adreno_dev),

		gmu_core_regwrite(KGSL_DEVICE(adreno_dev),
@@ -1791,7 +1791,7 @@ int adreno_zap_shader_load(struct adreno_device *adreno_dev, 
 * Return: IRQ_HANDLED if one or more interrupt callbacks were called.

 * Return: IRQ_HANDLED if one or more interrupt callbacks were called.

 */

 */

irqreturn_t adreno_irq_callbacks(struct adreno_device *adreno_dev,

irqreturn_t adreno_irq_callbacks(struct adreno_device *adreno_dev,

		struct adreno_irq_funcs *funcs, u32 status);

		const struct adreno_irq_funcs *funcs, u32 status);









/**

/**

drivers/gpu/msm/adreno_a3xx.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -793,7 +793,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) 
	 (1 << A3XX_INT_CP_AHB_ERROR_HALT) |     \

	 (1 << A3XX_INT_CP_AHB_ERROR_HALT) |     \

	 (1 << A3XX_INT_UCHE_OOB_ACCESS))

	 (1 << A3XX_INT_UCHE_OOB_ACCESS))





static struct adreno_irq_funcs a3xx_irq_funcs[32] = {

static const struct adreno_irq_funcs a3xx_irq_funcs[32] = {

	ADRENO_IRQ_CALLBACK(NULL),                    /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(NULL),                    /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(a3xx_err_callback),  /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(a3xx_err_callback),  /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(NULL),  /* 2 - RBBM_REG_TIMEOUT */

	ADRENO_IRQ_CALLBACK(NULL),  /* 2 - RBBM_REG_TIMEOUT */
@@ -1241,7 +1241,7 @@ static int a3xx_clear_pending_transactions(struct adreno_device *adreno_dev) 
	return ret;

	return ret;

}

}





struct adreno_gpudev adreno_a3xx_gpudev = {

const struct adreno_gpudev adreno_a3xx_gpudev = {

	.reg_offsets = a3xx_register_offsets,

	.reg_offsets = a3xx_register_offsets,

	.ft_perf_counters = a3xx_ft_perf_counters,

	.ft_perf_counters = a3xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),

	.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),

drivers/gpu/msm/adreno_a5xx.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -2343,7 +2343,7 @@ u64 a5xx_read_alwayson(struct adreno_device *adreno_dev) 
}

}









static struct adreno_irq_funcs a5xx_irq_funcs[32] = {

static const struct adreno_irq_funcs a5xx_irq_funcs[32] = {

	ADRENO_IRQ_CALLBACK(NULL),              /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(NULL),              /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 2 - RBBM_TRANSFER_TIMEOUT */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 2 - RBBM_TRANSFER_TIMEOUT */
@@ -2646,7 +2646,7 @@ static struct adreno_coresight a5xx_coresight = { 
};

};

#endif

#endif





struct adreno_gpudev adreno_a5xx_gpudev = {

const struct adreno_gpudev adreno_a5xx_gpudev = {

	.reg_offsets = a5xx_register_offsets,

	.reg_offsets = a5xx_register_offsets,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a5xx_coresight},

	.coresight = {&a5xx_coresight},

drivers/gpu/msm/adreno_a6xx.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -1585,7 +1585,7 @@ static void a6xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit) 
	adreno_dispatcher_schedule(device);

	adreno_dispatcher_schedule(device);

}

}





static struct adreno_irq_funcs a6xx_irq_funcs[32] = {

static const struct adreno_irq_funcs a6xx_irq_funcs[32] = {

	ADRENO_IRQ_CALLBACK(NULL),              /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(NULL),              /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(NULL), /* 2 - UNUSED */

	ADRENO_IRQ_CALLBACK(NULL), /* 2 - UNUSED */
@@ -2123,7 +2123,7 @@ int a6xx_probe_common(struct platform_device *pdev, 
	struct	adreno_device *adreno_dev, u32 chipid,

	struct	adreno_device *adreno_dev, u32 chipid,

	const struct adreno_gpu_core *gpucore)

	const struct adreno_gpu_core *gpucore)

{

{

	struct adreno_gpudev *gpudev = gpucore->gpudev;

	const struct adreno_gpudev *gpudev = gpucore->gpudev;





	adreno_dev->gpucore = gpucore;

	adreno_dev->gpucore = gpucore;

	adreno_dev->chipid = chipid;

	adreno_dev->chipid = chipid;
@@ -2464,7 +2464,7 @@ static int a6xx_clear_pending_transactions(struct adreno_device *adreno_dev) 
	return a6xx_halt_gbif(adreno_dev);

	return a6xx_halt_gbif(adreno_dev);

}

}





struct adreno_gpudev adreno_a6xx_gpudev = {

const struct adreno_gpudev adreno_a6xx_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_probe,

	.probe = a6xx_probe,

	.start = a6xx_start,

	.start = a6xx_start,
@@ -2499,7 +2499,7 @@ struct adreno_gpudev adreno_a6xx_gpudev = { 
	.clear_pending_transactions = a6xx_clear_pending_transactions,

	.clear_pending_transactions = a6xx_clear_pending_transactions,

};

};





struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {

const struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_hwsched_probe,

	.probe = a6xx_hwsched_probe,

	.snapshot = a6xx_hwsched_snapshot,

	.snapshot = a6xx_hwsched_snapshot,
@@ -2515,7 +2515,7 @@ struct adreno_gpudev adreno_a6xx_hwsched_gpudev = { 
	.power_ops = &a6xx_hwsched_power_ops,

	.power_ops = &a6xx_hwsched_power_ops,

};

};





struct adreno_gpudev adreno_a6xx_gmu_gpudev = {

const struct adreno_gpudev adreno_a6xx_gmu_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_gmu_device_probe,

	.probe = a6xx_gmu_device_probe,

	.start = a6xx_start,

	.start = a6xx_start,
@@ -2546,7 +2546,7 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = { 
	.power_ops = &a6xx_gmu_power_ops,

	.power_ops = &a6xx_gmu_power_ops,

};

};





struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {

const struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_rgmu_device_probe,

	.probe = a6xx_rgmu_device_probe,

	.start = a6xx_start,

	.start = a6xx_start,
@@ -2577,7 +2577,7 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = { 
	.power_ops = &a6xx_rgmu_power_ops,

	.power_ops = &a6xx_rgmu_power_ops,

};

};





struct adreno_gpudev adreno_a619_holi_gpudev = {

const struct adreno_gpudev adreno_a619_holi_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_probe,

	.probe = a6xx_probe,

	.start = a6xx_start,

	.start = a6xx_start,
@@ -2612,7 +2612,7 @@ struct adreno_gpudev adreno_a619_holi_gpudev = { 
	.clear_pending_transactions = a6xx_clear_pending_transactions,

	.clear_pending_transactions = a6xx_clear_pending_transactions,

};

};





struct adreno_gpudev adreno_a630_gpudev = {

const struct adreno_gpudev adreno_a630_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_gmu_device_probe,

	.probe = a6xx_gmu_device_probe,

	.start = a6xx_start,

	.start = a6xx_start,