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Commit dc8ae677 authored by Leo Liu's avatar Leo Liu Committed by Alex Deucher
Browse files

drm/amdgpu/VCN: implement indirect DPG SRAM mode 



SRAM will be programmed by PSP

Signed-off-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a77b9fdf

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+3 −0
Original line number Diff line number Diff line
@@ -111,6 +111,9 @@ 
				(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | 			\

				 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | 			\

				 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); 		\

		} else { 									\

			*adev->vcn.dpg_sram_curr_addr++ = offset; 				\

			*adev->vcn.dpg_sram_curr_addr++ = value; 				\

		} 										\

	} while (0)

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+50 −19
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "soc15.h"

#include "soc15d.h"

#include "amdgpu_pm.h"

#include "amdgpu_psp.h"



#include "vcn/vcn_2_0_0_offset.h"

#include "vcn/vcn_2_0_0_sh_mask.h"
@@ -407,6 +408,7 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec 


	/* cache window 0: fw */

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (!indirect) {

			WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
@@ -415,6 +417,14 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec 
				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

				UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		} else {

			WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

				UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		}

		offset = 0;

	} else {

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
@@ -429,10 +439,15 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec 
			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);

	}



	if (!indirect)

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

	else

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);



	/* cache window 1: stack */

	if (!indirect) {

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
@@ -441,6 +456,14 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec 
			upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	} else {

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	}

	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(

		UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
@@ -911,6 +934,9 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 
	tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;

	WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);



	if (indirect)

		adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr;



	/* enable clock gating */

	vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
@@ -982,6 +1008,11 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 
		UVD, 0, mmUVD_MASTINT_EN),

		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);



	if (indirect)

		psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr,

			(uint32_t)((uint64_t)adev->vcn.dpg_sram_curr_addr -

			(uint64_t)adev->vcn.dpg_sram_cpu_addr));



	/* force RBC into idle state */

	rb_bufsz = order_base_2(ring->ring_size);

	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
@@ -1027,7 +1058,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev) 
		amdgpu_dpm_enable_uvd(adev, true);



	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {

		r = vcn_v2_0_start_dpg_mode(adev, 0);

		r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);

		if (r)

			return r;

		goto jpeg;