Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dc8385f0 authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller
Browse files

drivers: net: xgene: Preparing for adding SGMII based 1GbE



- Added link_state function pointer to the xgene__mac_ops structure
- Moved ring manager (pdata->rm) assignment to xgene_enet_setup_ops
- Removed unused variable (pdata->phy_addr) and macro (FULL_DUPLEX)

Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarKeyur Chudgar <kchudgar@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4c2e7f09
Loading
Loading
Loading
Loading
+0 −1
Original line number Diff line number Diff line
@@ -410,7 +410,6 @@ static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
		(dev_addr[1] << 8) | dev_addr[0];
	addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
	addr1 |= pdata->phy_addr & 0xFFFF;

	xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0);
	xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1);
+0 −1
Original line number Diff line number Diff line
@@ -179,7 +179,6 @@ enum xgene_enet_rm {
#define TUND_ADDR			0x4a

#define TSO_IPPROTO_TCP			1
#define	FULL_DUPLEX			2

#define USERINFO_POS			0
#define USERINFO_LEN			32
+5 −3
Original line number Diff line number Diff line
@@ -833,11 +833,9 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
	if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) {
		pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET;
		pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET;
		pdata->rm = RM3;
	} else {
		pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
		pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
		pdata->rm = RM0;
	}
	pdata->rx_buff_cnt = NUM_PKT_BUF;

@@ -881,10 +879,12 @@ static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
	case PHY_INTERFACE_MODE_RGMII:
		pdata->mac_ops = &xgene_gmac_ops;
		pdata->port_ops = &xgene_gport_ops;
		pdata->rm = RM3;
		break;
	default:
		pdata->mac_ops = &xgene_xgmac_ops;
		pdata->port_ops = &xgene_xgport_ops;
		pdata->rm = RM0;
		break;
	}
}
@@ -895,6 +895,7 @@ static int xgene_enet_probe(struct platform_device *pdev)
	struct xgene_enet_pdata *pdata;
	struct device *dev = &pdev->dev;
	struct napi_struct *napi;
	struct xgene_mac_ops *mac_ops;
	int ret;

	ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata));
@@ -937,10 +938,11 @@ static int xgene_enet_probe(struct platform_device *pdev)

	napi = &pdata->rx_ring->napi;
	netif_napi_add(ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT);
	mac_ops = pdata->mac_ops;
	if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
		ret = xgene_enet_mdio_config(pdata);
	else
		INIT_DELAYED_WORK(&pdata->link_work, xgene_enet_link_state);
		INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state);

	return ret;
err:
+1 −1
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ struct xgene_mac_ops {
	void (*tx_disable)(struct xgene_enet_pdata *pdata);
	void (*rx_disable)(struct xgene_enet_pdata *pdata);
	void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
	void (*link_state)(struct work_struct *work);
};

struct xgene_port_ops {
@@ -109,7 +110,6 @@ struct xgene_enet_pdata {
	void __iomem *base_addr;
	void __iomem *ring_csr_addr;
	void __iomem *ring_cmd_addr;
	u32 phy_addr;
	int phy_mode;
	enum xgene_enet_rm rm;
	struct rtnl_link_stats64 stats;
+2 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
	clk_disable_unprepare(pdata->clk);
}

void xgene_enet_link_state(struct work_struct *work)
static void xgene_enet_link_state(struct work_struct *work)
{
	struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
					 struct xgene_enet_pdata, link_work);
@@ -322,6 +322,7 @@ struct xgene_mac_ops xgene_xgmac_ops = {
	.rx_disable = xgene_xgmac_rx_disable,
	.tx_disable = xgene_xgmac_tx_disable,
	.set_mac_addr = xgene_xgmac_set_mac_addr,
	.link_state = xgene_enet_link_state
};

struct xgene_port_ops xgene_xgport_ops = {
Loading