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Commit dc37fec4 authored by Rhyland Klein's avatar Rhyland Klein Committed by Thierry Reding
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clk: tegra: periph: Add new periph clks and muxes for Tegra210



Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.

Tegra210 has some differences in the PLLP clock tree:
- Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO,
  and PLLP_OUT_XUSB.
- PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO.
- PLLP_OUT4 is the child of PLLP_OUT_CPU.

Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210.

Including work by Andrew Bresticker <abrestic@chromium.org> and
Bill Huang <bilhuang@nvidia.com>.

Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 385f9adf
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+67 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ enum clk_id {
	tegra_clk_amx1,
	tegra_clk_apbdma,
	tegra_clk_apbif,
	tegra_clk_ape,
	tegra_clk_audio0,
	tegra_clk_audio0_2x,
	tegra_clk_audio0_mux,
@@ -38,6 +39,7 @@ enum clk_id {
	tegra_clk_cile,
	tegra_clk_clk_32k,
	tegra_clk_clk72Mhz,
	tegra_clk_clk72Mhz_8,
	tegra_clk_clk_m,
	tegra_clk_clk_m_div2,
	tegra_clk_clk_m_div4,
@@ -51,17 +53,21 @@ enum clk_id {
	tegra_clk_cml1,
	tegra_clk_csi,
	tegra_clk_csite,
	tegra_clk_csite_8,
	tegra_clk_csus,
	tegra_clk_cve,
	tegra_clk_dam0,
	tegra_clk_dam1,
	tegra_clk_dam2,
	tegra_clk_d_audio,
	tegra_clk_dbgapb,
	tegra_clk_dds,
	tegra_clk_dfll_ref,
	tegra_clk_dfll_soc,
	tegra_clk_disp1,
	tegra_clk_disp1_8,
	tegra_clk_disp2,
	tegra_clk_disp2_8,
	tegra_clk_dp2,
	tegra_clk_dpaux,
	tegra_clk_dsialp,
@@ -71,6 +77,7 @@ enum clk_id {
	tegra_clk_dtv,
	tegra_clk_emc,
	tegra_clk_entropy,
	tegra_clk_entropy_8,
	tegra_clk_epp,
	tegra_clk_epp_8,
	tegra_clk_extern1,
@@ -85,12 +92,16 @@ enum clk_id {
	tegra_clk_gr3d_8,
	tegra_clk_hclk,
	tegra_clk_hda,
	tegra_clk_hda_8,
	tegra_clk_hda2codec_2x,
	tegra_clk_hda2codec_2x_8,
	tegra_clk_hda2hdmi,
	tegra_clk_hdmi,
	tegra_clk_hdmi_audio,
	tegra_clk_host1x,
	tegra_clk_host1x_8,
	tegra_clk_host1x_9,
	tegra_clk_hsic_trk,
	tegra_clk_i2c1,
	tegra_clk_i2c2,
	tegra_clk_i2c3,
@@ -110,11 +121,14 @@ enum clk_id {
	tegra_clk_i2s4_sync,
	tegra_clk_isp,
	tegra_clk_isp_8,
	tegra_clk_isp_9,
	tegra_clk_ispb,
	tegra_clk_kbc,
	tegra_clk_kfuse,
	tegra_clk_la,
	tegra_clk_maud,
	tegra_clk_mipi,
	tegra_clk_mipibif,
	tegra_clk_mipi_cal,
	tegra_clk_mpe,
	tegra_clk_mselect,
@@ -124,11 +138,16 @@ enum clk_id {
	tegra_clk_ndspeed,
	tegra_clk_ndspeed_8,
	tegra_clk_nor,
	tegra_clk_nvdec,
	tegra_clk_nvenc,
	tegra_clk_nvjpg,
	tegra_clk_owr,
	tegra_clk_owr_8,
	tegra_clk_pcie,
	tegra_clk_pclk,
	tegra_clk_pll_a,
	tegra_clk_pll_a_out0,
	tegra_clk_pll_a1,
	tegra_clk_pll_c,
	tegra_clk_pll_c2,
	tegra_clk_pll_c3,
@@ -140,15 +159,22 @@ enum clk_id {
	tegra_clk_pll_d_out0,
	tegra_clk_pll_dp,
	tegra_clk_pll_e_out0,
	tegra_clk_pll_g_ref,
	tegra_clk_pll_m,
	tegra_clk_pll_m_out1,
	tegra_clk_pll_mb,
	tegra_clk_pll_p,
	tegra_clk_pll_p_out1,
	tegra_clk_pll_p_out2,
	tegra_clk_pll_p_out2_int,
	tegra_clk_pll_p_out3,
	tegra_clk_pll_p_out4,
	tegra_clk_pll_p_out4_cpu,
	tegra_clk_pll_p_out5,
	tegra_clk_pll_p_out_hsio,
	tegra_clk_pll_p_out_xusb,
	tegra_clk_pll_p_out_cpu,
	tegra_clk_pll_p_out_adsp,
	tegra_clk_pll_ref,
	tegra_clk_pll_re_out,
	tegra_clk_pll_re_vco,
@@ -160,53 +186,80 @@ enum clk_id {
	tegra_clk_pll_x,
	tegra_clk_pll_x_out0,
	tegra_clk_pwm,
	tegra_clk_qspi,
	tegra_clk_rtc,
	tegra_clk_sata,
	tegra_clk_sata_8,
	tegra_clk_sata_cold,
	tegra_clk_sata_oob,
	tegra_clk_sata_oob_8,
	tegra_clk_sbc1,
	tegra_clk_sbc1_8,
	tegra_clk_sbc1_9,
	tegra_clk_sbc2,
	tegra_clk_sbc2_8,
	tegra_clk_sbc2_9,
	tegra_clk_sbc3,
	tegra_clk_sbc3_8,
	tegra_clk_sbc3_9,
	tegra_clk_sbc4,
	tegra_clk_sbc4_8,
	tegra_clk_sbc4_9,
	tegra_clk_sbc5,
	tegra_clk_sbc5_8,
	tegra_clk_sbc6,
	tegra_clk_sbc6_8,
	tegra_clk_sclk,
	tegra_clk_sdmmc_legacy,
	tegra_clk_sdmmc1,
	tegra_clk_sdmmc1_8,
	tegra_clk_sdmmc1_9,
	tegra_clk_sdmmc2,
	tegra_clk_sdmmc2_8,
	tegra_clk_sdmmc2_9,
	tegra_clk_sdmmc3,
	tegra_clk_sdmmc3_8,
	tegra_clk_sdmmc3_9,
	tegra_clk_sdmmc4,
	tegra_clk_sdmmc4_8,
	tegra_clk_sdmmc4_9,
	tegra_clk_se,
	tegra_clk_soc_therm,
	tegra_clk_soc_therm_8,
	tegra_clk_sor0,
	tegra_clk_sor0_lvds,
	tegra_clk_sor1,
	tegra_clk_sor1_brick,
	tegra_clk_sor1_src,
	tegra_clk_spdif,
	tegra_clk_spdif_2x,
	tegra_clk_spdif_in,
	tegra_clk_spdif_in_8,
	tegra_clk_spdif_in_sync,
	tegra_clk_spdif_mux,
	tegra_clk_spdif_out,
	tegra_clk_timer,
	tegra_clk_trace,
	tegra_clk_tsec,
	tegra_clk_tsec_8,
	tegra_clk_tsecb,
	tegra_clk_tsensor,
	tegra_clk_tvdac,
	tegra_clk_tvo,
	tegra_clk_uarta,
	tegra_clk_uarta_8,
	tegra_clk_uartb,
	tegra_clk_uartb_8,
	tegra_clk_uartc,
	tegra_clk_uartc_8,
	tegra_clk_uartd,
	tegra_clk_uartd_8,
	tegra_clk_uarte,
	tegra_clk_uarte_8,
	tegra_clk_uartape,
	tegra_clk_usb2,
	tegra_clk_usb2_hsic_trk,
	tegra_clk_usb2_trk,
	tegra_clk_usb3,
	tegra_clk_usbd,
	tegra_clk_vcp,
@@ -216,22 +269,35 @@ enum clk_id {
	tegra_clk_vi,
	tegra_clk_vi_8,
	tegra_clk_vi_9,
	tegra_clk_vi_10,
	tegra_clk_vi_i2c,
	tegra_clk_vic03,
	tegra_clk_vic03_8,
	tegra_clk_vim2_clk,
	tegra_clk_vimclk_sync,
	tegra_clk_vi_sensor,
	tegra_clk_vi_sensor2,
	tegra_clk_vi_sensor_8,
	tegra_clk_vi_sensor_9,
	tegra_clk_vi_sensor2,
	tegra_clk_vi_sensor2_8,
	tegra_clk_xusb_dev,
	tegra_clk_xusb_dev_src,
	tegra_clk_xusb_dev_src_8,
	tegra_clk_xusb_falcon_src,
	tegra_clk_xusb_falcon_src_8,
	tegra_clk_xusb_fs_src,
	tegra_clk_xusb_gate,
	tegra_clk_xusb_host,
	tegra_clk_xusb_host_src,
	tegra_clk_xusb_host_src_8,
	tegra_clk_xusb_hs_src,
	tegra_clk_xusb_hs_src_4,
	tegra_clk_xusb_ss,
	tegra_clk_xusb_ss_src,
	tegra_clk_xusb_ss_src_8,
	tegra_clk_xusb_ss_div2,
	tegra_clk_xusb_ssp_src,
	tegra_clk_sclk_mux,
	tegra_clk_max,
};

+367 −4

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