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Commit dc12f20b authored by Masanari Iida's avatar Masanari Iida Committed by Jonathan Corbet
Browse files

Doc: powerpc: Fix typos in Documentation/powerpc 



This patch fix some spelling typo found in Documentation/powerpc.

Signed-off-by: default avatarMasanari Iida <standby24x7@gmail.com>
Acked-by: default avatarIan Munsie <imunsie@au1.ibm.com>
Signed-off-by: default avatarJonathan Corbet <corbet@lwn.net>
parent 9ba6e988

Documentation/powerpc/cxl.txt

+1 −1
Original line number Original line Diff line number Diff line
@@ -133,7 +133,7 @@ User API 
    The following file operations are supported on both slave and

    The following file operations are supported on both slave and

    master devices.

    master devices.





    A userspace library libcxl is avaliable here:

    A userspace library libcxl is available here:

	https://github.com/ibm-capi/libcxl

	https://github.com/ibm-capi/libcxl

    This provides a C interface to this kernel API.

    This provides a C interface to this kernel API.

Documentation/powerpc/dscr.txt

+3 −3
Original line number Original line Diff line number Diff line
@@ -4,7 +4,7 @@ 
DSCR register in powerpc allows user to have some control of prefetch of data

DSCR register in powerpc allows user to have some control of prefetch of data

stream in the processor. Please refer to the ISA documents or related manual

stream in the processor. Please refer to the ISA documents or related manual

for more detailed information regarding how to use this DSCR to attain this

for more detailed information regarding how to use this DSCR to attain this

control of the pefetches . This document here provides an overview of kernel

control of the prefetches . This document here provides an overview of kernel

support for DSCR, related kernel objects, it's functionalities and exported

support for DSCR, related kernel objects, it's functionalities and exported

user interface.

user interface.
@@ -44,7 +44,7 @@ user interface. 
	value into every CPU's DSCR register right away and updates the current

	value into every CPU's DSCR register right away and updates the current

	thread's DSCR value as well.

	thread's DSCR value as well.





	Changing the CPU specif DSCR default value in the sysfs does exactly

	Changing the CPU specific DSCR default value in the sysfs does exactly

	the same thing as above but unlike the global one above, it just changes

	the same thing as above but unlike the global one above, it just changes

	stuff for that particular CPU instead for all the CPUs on the system.

	stuff for that particular CPU instead for all the CPUs on the system.
@@ -62,7 +62,7 @@ user interface. 




	Accessing DSCR through user level SPR (0x03) from user space will first

	Accessing DSCR through user level SPR (0x03) from user space will first

	create a facility unavailable exception. Inside this exception handler

	create a facility unavailable exception. Inside this exception handler

	all mfspr isntruction based read attempts will get emulated and returned

	all mfspr instruction based read attempts will get emulated and returned

	where as the first mtspr instruction based write attempts will enable

	where as the first mtspr instruction based write attempts will enable

	the DSCR facility for the next time around (both for read and write) by

	the DSCR facility for the next time around (both for read and write) by

	setting DSCR facility in the FSCR register.

	setting DSCR facility in the FSCR register.

Documentation/powerpc/qe_firmware.txt

+1 −1
Original line number Original line Diff line number Diff line
@@ -117,7 +117,7 @@ specific been defined. This table describes the structure. 
Extended Modes

Extended Modes





This is a double word bit array (64 bits) that defines special functionality

This is a double word bit array (64 bits) that defines special functionality

which has an impact on the softwarew drivers.  Each bit has its own impact

which has an impact on the software drivers.  Each bit has its own impact

and has special instructions for the s/w associated with it.  This structure is

and has special instructions for the s/w associated with it.  This structure is

described in this table:

described in this table: