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Commit dbd764e9 authored by Kornel Dulęba's avatar Kornel Dulęba Committed by Greg Kroah-Hartman
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pinctrl: amd: Disable and mask interrupts on resume 



[ Upstream commit b26cd9325be4c1fcd331b77f10acb627c560d4d7 ]

This fixes a similar problem to the one observed in:
commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe").

On some systems, during suspend/resume cycle firmware leaves
an interrupt enabled on a pin that is not used by the kernel.
This confuses the AMD pinctrl driver and causes spurious interrupts.

The driver already has logic to detect if a pin is used by the kernel.
Leverage it to re-initialize interrupt fields of a pin only if it's not
used by us.

Cc: stable@vger.kernel.org
Fixes: dbad75dd ("pinctrl: add AMD GPIO driver support.")
Signed-off-by: default avatarKornel Dulęba <korneld@chromium.org>
Link: https://lore.kernel.org/r/20230320093259.845178-1-korneld@chromium.org


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent dd7e19f9

drivers/pinctrl/pinctrl-amd.c

+20 −16
Original line number Diff line number Diff line
@@ -770,32 +770,34 @@ static const struct pinconf_ops amd_pinconf_ops = { 
	.pin_config_group_set = amd_pinconf_group_set,

};



static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)

static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin)

{

	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;

	const struct pin_desc *pd;

	unsigned long flags;

	u32 pin_reg, mask;

	int i;



	mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |

		BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |

		BIT(WAKE_CNTRL_OFF_S4);



	for (i = 0; i < desc->npins; i++) {

		int pin = desc->pins[i].number;

		const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);



	pd = pin_desc_get(gpio_dev->pctrl, pin);

	if (!pd)

			continue;

		return;



	raw_spin_lock_irqsave(&gpio_dev->lock, flags);



		pin_reg = readl(gpio_dev->base + i * 4);

	pin_reg = readl(gpio_dev->base + pin * 4);

	pin_reg &= ~mask;

		writel(pin_reg, gpio_dev->base + i * 4);



	writel(pin_reg, gpio_dev->base + pin * 4);

	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);

}



static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)

{

	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;

	int i;



	for (i = 0; i < desc->npins; i++)

		amd_gpio_irq_init_pin(gpio_dev, i);

}



#ifdef CONFIG_PM_SLEEP
@@ -848,8 +850,10 @@ static int amd_gpio_resume(struct device *dev) 
	for (i = 0; i < desc->npins; i++) {

		int pin = desc->pins[i].number;



		if (!amd_gpio_should_save(gpio_dev, pin))

		if (!amd_gpio_should_save(gpio_dev, pin)) {

			amd_gpio_irq_init_pin(gpio_dev, pin);

			continue;

		}



		raw_spin_lock_irqsave(&gpio_dev->lock, flags);

		gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;