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Commit dbd1a4fd authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Greg Kroah-Hartman
Browse files

clk: socfpga: use clk_hw_register for a5/c5 



[ Upstream commit 2c2b9c6067170de2a63e7e3d9f5bb205b870de7c ]

As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver
to use the clk_hw registration method.

Suggested-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-1-dinguyen@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Stable-dep-of: 0b8ba891ad4d ("clk: socfpga: Fix memory leak in socfpga_gate_init()")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 49513eab

drivers/clk/socfpga/clk-gate.c

+7 −4
Original line number Diff line number Diff line
@@ -174,13 +174,14 @@ void __init socfpga_gate_init(struct device_node *node) 
	u32 div_reg[3];

	u32 clk_phase[2];

	u32 fixed_div;

	struct clk *clk;

	struct clk_hw *hw_clk;

	struct socfpga_gate_clk *socfpga_clk;

	const char *clk_name = node->name;

	const char *parent_name[SOCFPGA_MAX_PARENTS];

	struct clk_init_data init;

	struct clk_ops *ops;

	int rc;

	int err;



	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);

	if (WARN_ON(!socfpga_clk))
@@ -238,12 +239,14 @@ void __init socfpga_gate_init(struct device_node *node) 
	init.parent_names = parent_name;

	socfpga_clk->hw.hw.init = &init;



	clk = clk_register(NULL, &socfpga_clk->hw.hw);

	if (WARN_ON(IS_ERR(clk))) {

	hw_clk = &socfpga_clk->hw.hw;



	err = clk_hw_register(NULL, hw_clk);

	if (err) {

		kfree(socfpga_clk);

		return;

	}

	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);

	rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);

	if (WARN_ON(rc))

		return;

}

drivers/clk/socfpga/clk-periph.c

+4 −4
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ static __init void __socfpga_periph_init(struct device_node *node, 
	const struct clk_ops *ops)

{

	u32 reg;

	struct clk *clk;

	struct clk_hw *hw_clk;

	struct socfpga_periph_clk *periph_clk;

	const char *clk_name = node->name;

	const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -94,13 +94,13 @@ static __init void __socfpga_periph_init(struct device_node *node, 
	init.parent_names = parent_name;



	periph_clk->hw.hw.init = &init;

	hw_clk = &periph_clk->hw.hw;



	clk = clk_register(NULL, &periph_clk->hw.hw);

	if (WARN_ON(IS_ERR(clk))) {

	if (clk_hw_register(NULL, hw_clk)) {

		kfree(periph_clk);

		return;

	}

	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);

	rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);

}



void __init socfpga_periph_init(struct device_node *node)

drivers/clk/socfpga/clk-pll.c

+11 −7
Original line number Diff line number Diff line
@@ -70,16 +70,18 @@ static struct clk_ops clk_pll_ops = { 
	.get_parent = clk_pll_get_parent,

};



static __init struct clk *__socfpga_pll_init(struct device_node *node,

static __init struct clk_hw *__socfpga_pll_init(struct device_node *node,

	const struct clk_ops *ops)

{

	u32 reg;

	struct clk *clk;

	struct clk_hw *hw_clk;

	struct socfpga_pll *pll_clk;

	const char *clk_name = node->name;

	const char *parent_name[SOCFPGA_MAX_PARENTS];

	struct clk_init_data init;

	struct device_node *clkmgr_np;

	int rc;

	int err;



	of_property_read_u32(node, "reg", &reg);
@@ -107,13 +109,15 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, 
	clk_pll_ops.enable = clk_gate_ops.enable;

	clk_pll_ops.disable = clk_gate_ops.disable;



	clk = clk_register(NULL, &pll_clk->hw.hw);

	if (WARN_ON(IS_ERR(clk))) {

	hw_clk = &pll_clk->hw.hw;



	err = clk_hw_register(NULL, hw_clk);

	if (err) {

		kfree(pll_clk);

		return NULL;

		return ERR_PTR(err);

	}

	of_clk_add_provider(node, of_clk_src_simple_get, clk);

	return clk;

	rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);

	return hw_clk;

}



void __init socfpga_pll_init(struct device_node *node)